Wednesday, July 20th 2011

Intel Mulls Propagating PCI-Express 2.0 x2 Interface

PCI-Express x1 met its match with the recent flood of devices such as 2-port SATA 6 Gbps and USB 3.0 controller chips that maintain their tiny package sizes thanks to a single-lane PCI-Express bus connection. The single-lane connection is already saturated with these kinds of devices: SATA 6 Gbps is moot with 250 MB/s per direction bandwidth of PCI-E 1.1, and could face bottlenecks with 500 MB/s of PCI-E 2.0, it is a similar case with USB 3.0 controllers. Use of PCI-Expresss x4, the bigger PCI-E bus standard, is a bad option as it increases PCI-E data pins by four times (significantly impacting chip package sizes), while eating into the limited lane budget of today's desktop chipsets.

The next best thing is PCI-Express 2.0 x2. While 2-lane PCI-Express is hypothetically possible, it has never been implemented by motherboard manufactures, neither on client, nor enterprise platforms. PCI-Express' parent organisation PCI-SIG doesn't have a slot or port specification for PCI-E x2, either. Intel seems to be of the idea that PCI-Express 2.0 x2 will provide immediate relief to manufacturers of small-footprint devices such as inexpensive third-party USB 3.0 and SATA 6 Gbps controllers, it provides a total of 2 GB/s bandwidth, 1 GB/s per direction, which greatly alleviates bandwidth bottlenecks, while not significanly increasing chip pin-counts. PCI-Express 3.0 is still in its infancy, while implementing PCI-Express 2.0 x2 is the easier, short-term solution. It will cause minimal R&D overhead on manufacturers to implement it. PCI-E 2.0 x2 will fit nicely into the limited lane budget of today's desktop chipsets.Source: VR-Zone
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29 Comments on Intel Mulls Propagating PCI-Express 2.0 x2 Interface

#3
The Von Matrices
I always wondered why x2 was missing since the link widths were 2^n. The addition seems logical to me.
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#4
The Von Matrices
by: FordGT90Concept
Boo, use x4.
Since Intel's mainstream chipsets have only 8 non-graphics PCIe lanes and AMD's mainsteam chipsets have only 6 non-graphics PCIe lanes, having PCIe x4 for devices isn't feasible unless you're happy with only 1 add-in controller and nothing else on your board.
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#5
Swamp Monster
PCI-Express 2.0 x2 - another standard we don't need. Why not use PCI-E 3.0? "PCI-Express 3.0 is still in its infancy" is not argument good enough. If they have used it istead, then it would not be in it's infancy anymore.:shadedshu
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#6
btarunr
Editor & Senior Moderator
by: Swamp Monster
PCI-Express 2.0 x2 - another standard we don't need. Why not use PCI-E 3.0? "PCI-Express 3.0 is still in its infancy" is not argument good enough. If they have used it istead, then it would not be in it's infancy anymore.:shadedshu
Because companies as big as AMD, NVIDIA, and Intel can afford to test the waters with PCI-E 3.0, and bear the brunt in the event of a specifications flaw by shelling out millions of dollars in product recalls. Companies as small as JMicron, Renesas, VLI (VIA), etc., can't. Hence PCI-Express 3.0 is in its infancy. It took a long while after big companies implemented PCI-E 2.0 before small manufacturers followed. Hence, Intel wants to make things easy for itself as a desktop chipset manufacturer, and for those smaller companies.
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#7
D4S4
this is surprisingly nice (coming from a big evil corporation intel is)
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#8
btarunr
Editor & Senior Moderator
by: D4S4
this is surprisingly nice (coming from a big evil corporation intel is)
One possibility is that Intel wants to spread cheap Thunderbolt controllers, and PCI-E 2.0 x1 is too little interface bandwidth, PCI-E 2.0 x4 is too many pins.
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#9
R_1
Use PCI-E 3.0 x1 instead!!!
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#10
arnoo1
ow that's is why my corsair force3 120gb does a write speed of just 242mb/s instead the 500mb/s it's should do lol, i already know that because of maban|(thanks)

now i have to wait for my gigabyte ga-z68x ud4 b3 and 2600k
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#11
Jizzler
I'd think a little more positively about this if I was hearing it from the companies or users who are supposedly affected. Otherwise, it reeks of evil ploy. Short term solutions have a tendency to be more trouble than they're worth.
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#12
FordGT90Concept
"I go fast!1!11!1!"
by: The Von Matrices
Since Intel's mainstream chipsets have only 8 non-graphics PCIe lanes and AMD's mainsteam chipsets have only 6 non-graphics PCIe lanes, having PCIe x4 for devices isn't feasible unless you're happy with only 1 add-in controller and nothing else on your board.
Just because it takes an x4 slot doesn't mean it needs four electrical lanes to it. There's slots out now that have a x4 slot but only x1 electrical. Likewise, there's x16 slots with x8 electrical.


If they want to add x2 to the PCI Express 3.0 standard, no one will really care. Adding it to PCI Express 2.0 though is a bad idea.
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#13
btarunr
Editor & Senior Moderator
by: FordGT90Concept
Just because it takes an x4 slot doesn't mean it needs four electrical lanes to it. There's slots out now that have a x4 slot but only x1 electrical.
And you end up with x1 bandwidth.
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#14
FordGT90Concept
"I go fast!1!11!1!"
Well, you're screwed either way. Either they need to put more lanes in the chipsets so they can power an x4 slot or they need to break the PCI Express 2.0 standard. Intel would rather break something that is perfectly fine and put a few more cents worth into their chipsets.

Like I said, they should add x2 to PCI Express 3.0 and then push for using it. It makes no sense to revise a standard whom's days are already numbered.
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#15
btarunr
Editor & Senior Moderator
No, you're not screwed either way. Currently, the 8 lanes of a Cougar Point can either be arranged as [4 * x1 + 1 * x4] or [8 * x1] port configurations. If you are dedicating that x4 to a single device that doesn't need 4 GB/s (2 GB/s /direction), you're wasing lanes. Grouping them as x2 is just organising it in a better way.

Third-party GbE PHY chips don't use Cougar Point's GbE port (PCI-E 1.1 x1 @ 50 MHz), they take up one of those eight PCI-E x1 lanes, if you give away that PCI-E 2.0 x4 to a single device, you're left with just 3 lanes to offer as expansion slots or drive other onboard devices.

"Putting more lanes on the chipset" means designing a new chipset right now. Not viable.

Moving to PCI-E 3.0 would mean that Intel has to redesign a chipset, plus small manufacturers like JMicron have to spend tons of money designing for a new PCI-E specification, and carrying the risk of using a specification that hasn't been validated in the market by much bigger companies (like NVIDIA, AMD, etc.). This is something small companies won't do. So the easiest solution is PCI-E 2.0 x2. There's minimal R&D and risk by both parties.
Posted on Reply
#16
FordGT90Concept
"I go fast!1!11!1!"
by: btarunr
"Putting more lanes on the chipset" means designing a new chipset right now. Not viable.
What I meant was stop selling chipsets that don't have enough lanes to handle basic user requirements.


by: btarunr
Moving to PCI-E 3.0 would mean that Intel has to redesign a chipset, plus small manufacturers like JMicron have to spend tons of money designing for a new PCI-E specification, and carrying the risk of using a specification that hasn't been validated in the market by much bigger companies (like NVIDIA, AMD, etc.). This is something small companies won't do. So the easiest solution is PCI-E 2.0 x2. There's minimal R&D and risk by both parties.
I'd rather they release PCI Express 2.1 and 3.1 which have the x2 specification appended to it. That way you know what you have to look for if you intend to use an x2 device.
Posted on Reply
#17
Jizzler
I think that's a bad idea too. Another size? Not unless manufacturers adopt open-ended slots on more of their motherboards. And I'm sure they'll love having more skus to fit the needs of their users. Two x2 on model A, an x4, and two x1 on model B, etc.

Eventually all these smaller companies we've talked about will be on PCI 3.0, along with future chipsets with support. Shoe-horning in x2 now will undoubtedly extend the adoption of 3.0.

Luckily I think the premise of this mulling is weak and nothing will come of it :)
Posted on Reply
#18
DanTheBanjoman
Señor Moderator
by: The Von Matrices
I always wondered why x2 was missing since the link widths were 2^n. The addition seems logical to me.
Since when is it 2^n? I don't see why x3, x5, x6 etc aren't possible. In fact I'm pretty sure all that's required is a BIOS update for the motherboard and possibly a firmware update on the card to support any amount of lanes.
Posted on Reply
#19
FordGT90Concept
"I go fast!1!11!1!"
Yup, and this is why PCI-SIG opted only for x1, x4, x8, and x16. If it ain't enough, you jump up. I wonder if Intel consulted with PCI-SIG at all. I bet PCI-SIG would have answered "no" right away.
Posted on Reply
#20
btarunr
Editor & Senior Moderator
by: FordGT90Concept
Yup, and this is why PCI-SIG opted only for x1, x4, x8, and x16. If it ain't enough, you jump up. I wonder if Intel consulted with PCI-SIG at all. I bet PCI-SIG would have answered "no" right away.
Intel is a co-creator of PCI-Express. Intel, IBM, Dell, and HP are like veto powers in the PCI-SIG.
Posted on Reply
#21
newtekie1
Semi-Retired Folder
Just run an x4 link to a PCI-E switch and give yourself some more lanes. You aren't limitted just to the lanes provided by the chipset, bridge chips can and have been used to expand the lanes from the chipset to service more devices.

I'm pretty sure PLX already has products for this purpose. I believe they make a switch that can take an x4 link from the chipset, and output 3 x4 links, or 1 x4 link and 8 x1 links, or just 12 x1 links.

Yes, you can make the argument that all those links are still sharing the x4 uplink bandwidth and hence won't really gain a benefit from this. However, they work just like network switches. If only one device needs the x4 bandwidth, then it gets all that bandwidth. Yes, if more devices need that bandwidth they have to share it, but if you populate most of the links with low bandwidth devices such as onboard sound and USB2.0 controllers, and secondary LAN controllers, etc, then the high bandwidth device will get the bandwidth it needs.
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#22
FordGT90Concept
"I go fast!1!11!1!"
by: btarunr
Intel is a co-creator of PCI-Express. Intel, IBM, Dell, and HP are like veto powers in the PCI-SIG.
I could see Dell and HP saying no. I doubt IBM cares.
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#23
Hayder_Master
I see it's time to put SB agin, cuz many things now run over PCI-E so it should adding more PCI-E lines.
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#24
mastrdrver
Or you solve the problem with a board like the Asus P6T6 or P6T7. Sure you go through the NF200 chips, but you get a plethora of PCIe configuration options.

This is why I love my P6T6. My next board will also be a 'Workstation' type board with a similar 6/7x PCIe slots. I don't care for anything else after having one. PCI is going away and I see no reason to buy any add in card that does not have a PCIe interface. So why bother with a board that offers something I have no use for?

I know this isn't Intel, but they can bit me.
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#25
DanTheBanjoman
Señor Moderator
by: FordGT90Concept
I could see Dell and HP saying no. I doubt IBM cares.
What would be their arguments to be against it?
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