Wednesday, July 27th 2011

Intel Aims at 10 nm Processors by 2018

It's not just host nations of the Olympics that are decided almost decades in advance, but also Intel's silicon names and the fab process they're going to be built on. Intel has its plan for the greater part of this decade already charted out, well beyond the upcoming Ivy Bridge architecture. Intel follows the "tick-tock" product cycle, where every micro-architecture gets to be built on two succeeding fab processes, and every fab process getting to have two succeeding micro-architectures built on it, in succession. Westmere is an optical shrink of the Nehalem architecture, it was a "tick" for the 32 nm process, Sandy Bridge is its "tock", and a new architecture. Ivy Bridge is essentially an optical shrink of Sandy Bridge, it is the "tick" for 22 nm process.

Ivy Bridge will make its entry through the LGA1155 platform in 2012, it will make up the 2012 Core processor family. Haswell is the next-generation architecture that succeeds Sandy Bridge and IvyBridge, it will be built on the 22 nm process, and is expected to arrive in 2013. Roswell is its optical shrink to 14 nm, slated for 2014. Looking deep into the decade, there's Skylake architecture, that will span across 14 nm and 10 nm processes with Skymont. This model ensures that Intel has to upgrade its fabs every 2 or so years, an entirely new micro-architecture every 2 or so years as well, while providing optical shrinks every alternating year. Optical shrinks introduce new features, increased caches, and allow higher clock speeds. 10 nm for processors by 2018 sounds realistic looking at the advancement of NAND flash technologies that are pushing the boundaries of fab process development. NAND flash is much less complex than processor development, and hence serve as good precursors to a new process.

Source: ComputerBase.de
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64 Comments on Intel Aims at 10 nm Processors by 2018

#1
laszlo
and what after 10nm?

10nm will be a challenge to made as they all(not only intel) already have problems with 22nm....
Posted on Reply
#2
btarunr
Editor & Senior Moderator
They said sub-10 μm was going to be a problem. It turned out pretty well so far.
Posted on Reply
#3
entropy13
It would be even better if they look at other materials as well.
Posted on Reply
#4
hardcore_gamer
remember these things intel

hot electron effect
impact ionization
velocity saturation
drain induced barrier lowering
surface scattering
punchthrough
sub-threshold conduction


skylake-->skymont-->skynet
Posted on Reply
#5
Drone
Quantum tunnelling, where are yo
Posted on Reply
#6
Jonap_1st
by: hardcore_gamer
remember these things intel

hot electron effect
impact ionization
velocity saturation
drain induced barrier lowering
surface scattering
punchthrough
sub-threshold conduction


skylake-->skymont-->skynet
the judgement day will be closer than i thought..
Posted on Reply
#7

by: btarunr
They said sub-10 μm was going to be a problem. It turned out pretty well so far.
10 microns? As in 10,000nm? How long ago was that?
by: hardcore_gamer
remember these things intel

hot electron effect
impact ionization
velocity saturation
drain induced barrier lowering
surface scattering
punchthrough
sub-threshold conduction


skylake-->skymont-->skynet
I didn't understand any of that until "skynet", but at 10nm isn't easier to quote the trace width in atoms? I mean seriously. How do you make predictions like that with a straight face? Unless your margin for error is plus or minus 20 years.
#8
assaulter_99
Now I wonder where and when they will hit a wall.
Posted on Reply
#9
Trackr
The image shows Sandy Bridge as being a Q4 2011 release.

It was actually a Q1 2011 release.

Does that mean that the whole graph is ahead three quarters?
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#10
ensabrenoir
That timeline makes me think they already have this technology and they're just trying to figure out how to mass produce it cheaply/ cost effectively and yes intel= skynet. Tthe first attack will be on amd users world wide
Posted on Reply
#11
Benetanegia
by: Trackr
The image shows Sandy Bridge as being a Q4 2011 release.

It was actually a Q1 2011 release.

Does that mean that the whole graph is ahead three quarters?
Maybe/probably those are fiscal years, so it's not 3 quarters ahead, but 1 quarter behind (or just on time if they mean production instead of launch).
Posted on Reply
#13

by: Bjorn_Of_Iceland
cant wait for 1nm lol
2025. Obviously. At least based on their current timescale. All the universe bends to the will of Intel.
#14
Riotpump
by: twilyth
2025. Obviously. At least based on their current timescale. All the universe bends to the will of Intel.
I welcome our new Skynet Intel based overlords...
Posted on Reply
#15
Mussels
Moderprator
there was other threads about graphene being used in future CPU's since its thinner/smaller, and conducts electricity faster. that could well be a solution on how to best the 10nm barrier, once they get the tech ironed out fully.
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#16
MikeMurphy
Can't get much smaller than these molecules. 10nm is actually pretty close.
Posted on Reply
#17
btarunr
Editor & Senior Moderator
by: twilyth
10 microns? As in 10,000nm? How long ago was that?
My bad, 0.1 μm, or 100 nm.
Posted on Reply
#18
TheMailMan78
Big Member
10nm? I mean really? Thats pretty amazing if they can get em that small. If AMD's APU is successful by then I bet this road map changes dramatically. I mean if tablets and smartphones keep on this momentum they will HAVE to jump on the APU bandwagon more aggressively.


Also I wonder if it will run Crysis......Sorry I know thats 7 years early but we here on TPU are always cutting edge.

by: Mussels
there was other threads about graphene being used in future CPU's since its thinner/smaller, and conducts electricity faster. that could well be a solution on how to best the 10nm barrier, once they get the tech ironed out fully.
They got 7 years. Thats a several lifetimes in the tech world.
Posted on Reply
#19
Benetanegia
by: MikeMurphy
Can't get much smaller than these molecules. 10nm is actually pretty close.
They are close because they compare it in an order of magnitude basis I believe. Isn't Monocristaline Silicone's lattice spacing 0.5 nm? I don't really know about how semiconductors work at that level, but I would say that 10 cells (5nm?) should suffice, maybe even less. Also there's a bunch of atoms on every cristal cell so much smaller process (than 10nm) should be attainable from the POV of "molecule" size. Bear in mind I make this statement from my complete ignorance on the subject. I know basic electronics where the whole thing is abstract (holes) and physics where a single electron moves from one atom to another, I lack any knowledge of what really happens in the middle.

Graphene does have a much smaller lattice spacing iirc and I've seen claims of 2 layers of graphene being able to create a Cassimir Effect, so what about some science fiction and dreaming of autopowered chips (zero point energy)??!! :rockout:
Posted on Reply
#20
hardcore_gamer
by: Drone
Quantum tunnelling, where are yo
Hot electron effect is due to tunnelling


Using new materials like graphene may provide scaling beyond the capabilities of silicon, but still dynamic power consumption will be a problem.Adiabatic logic is a solution
Posted on Reply
#21

by: hardcore_gamer
Hot electron effect is due to tunnelling


Using new materials like graphene may provide scaling beyond the capabilities of silicon, but still dynamic power consumption will be a problem.Adiabatic logic is a solution
How is adiabatic logic going to either prevent random tunneling events or compensate for them. I would be extremely interested in that.
#22
Steevo
I'm not worried about the CPU's, I'm worried about the layers and traces on the PCB for the RAM, and in the motherboard.


Even if the traces in the CPU are 1nm they can make the insulator around and beside it 20nm if they need to, it just creates more heat as the electrical path is longer, and more latency from the same issue. However their 3D transistor should help with trace length, and thus electrical needs, and a shorter path also reduces the capacitive roll off charge. All that adds up to lower electrical needs, faster processing physically in the chip, and lower TDP.


The graphics card makers have already fought with memory management, I see this as being a plus for AMD, their dedicated cards have already taught them about the best way to perform on die termination, signaling, voltages, and path length. Intel had a bit of a issue with that on some chips, the termination voltage was burning out processors. They have probably already started work on the same issue as they make smaller and smaller traces on the CPU.
Posted on Reply
#23

The problem is that at a certain point you run into quantum effects that simply can't be controlled with traditional lithographic methods. Quantum tunneling for example - where an electron is supposed to be on one side of a dielectric but magically appears on the other. Tunneling is a probability function that varies with distance. When you start hitting distances that permit the effect, you're screwed and there's nothing you can do about it. I just don't happen to know at what level that starts to become a problem - or rather, an unmanageable problem
#24
TheMailMan78
Big Member
I doubt they will be using any "tunneling" within 7 years on a consumer product.
Posted on Reply
#25

I don't know that they'll ever "use it" so to speak, but that doesn't mean it won't be an issue. We may not be able to use lightning, but it can still be a serious pain in the ass.
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