Thursday, April 12th 2007

IBM Working on CPU Stacking

IBM Moves Moore's Law into the Third-Dimension

Armonk, NY - 12 Apr 2007: IBM (NYSE: IBM) today announced a breakthrough chip-stacking technology in a manufacturing environment that paves the way for three-dimensional chips that will extend Moore’s Law beyond its expected limits. The technology – called “through-silicon vias” -- allows different chip components to be packaged much closer together for faster, smaller, and lower-power systems.

The IBM breakthrough enables the move from horizontal 2-D chip layouts to 3-D chip stacking, which takes chips and memory devices that traditionally sit side by side on a silicon wafer and stacks them together on top of one another. The result is a compact sandwich of components that dramatically reduces the size of the overall chip package and boosts the speed at which data flows among the functions on the chip.

“This breakthrough is a result of more than a decade of pioneering research at IBM,” said Lisa Su, vice president, Semiconductor Research and Development Center, IBM. “This allows us to move 3-D chips from the 'lab to the fab' across a range of applications.”

The new IBM method eliminates the need for long-metal wires that connect today’s 2-D chips together, instead relying on through-silicon vias, which are essentially vertical connections etched through the silicon wafer and filled with metal. These vias allow multiple chips to be stacked together, allowing greater amounts of information to be passed between the chips.

The technique shortens the distance information on a chip needs to travel by 1000 times, and allows for the addition of up to 100 times more channels, or pathways, for that information to flow compared to 2-D chips.

IBM is already running chips using the through-silicon via technology in its manufacturing line and will begin making sample chips using this method available to customers in the second half of 2007, with production in 2008. The first application of this through-silicon via technology will be in wireless communications chips that will go into power amplifiers for wireless LAN and cellular applications. 3-D technology will also be applied to a wide range of chips, including those running now in IBM’s high-performance servers and supercomputers that power the world’s business, government and scientific efforts.

In particular, IBM is applying the new through-silicon-via technique in wireless communications chips, Power processors, Blue Gene supercomputer chips, and in high-bandwidth memory applications:
  • 3-D FOR WIRELESS COMMUNICATIONS TECHNOLOGY: IBM is using through-silicon via technology to improve power efficiency in silicon-germanium based wireless products up to 40 percent, which leads to longer battery life. The through-silicon via technology replaces the wire bonds that are less efficient at transferring signals off of the chip.
  • POWER PROCESSORS EXPLORE 3-D FOR POWER GRID STABILITY: As we increase the number of processor cores on chips, one of the limitations in performance is uniform power delivery to all parts of the chip. This technique puts the power closer to the cores and allows each core to have ample access to that power, increasing processor speed while reducing power consumption up to 20 percent.
  • BRINGING 3-D STACKING TO BLUE GENE SUPERCOMPUTING AND MEMORY ARRAYS: The most advanced version of 3-D chip stacking will allow high-performance chips to be stacked on top of each other, for example processor-on-processor or memory-on-processor. IBM is developing this advanced technology by converting the chip that currently powers the fastest computer in the world, the IBM Blue Gene supercomputer, into a 3-D stacked chip. IBM is also using 3-D technology to fundamentally change the way memory communicates with a microprocessor, by significantly enhancing the data flow between microprocessor and memory. This capability will enable a new generation of supercomputers. A prototype SRAM design using 3-D stacking technology is being fabricated in IBM's 300 mm production line using 65 nm- node technology.
Source: IBM
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8 Comments on IBM Working on CPU Stacking

#1
Zalmann
That's a great initiative. This will enable them to create more compact servers, or simply fit more in the same case. Imagine a 16core (4 x 4core) 1U rack server, then stack those. You can have the equivalent of a small data centre in a 6' rack.
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#2
Kreij
Senior Monkey Moderator
Intel has been commenting on a similar design with the cache stacked on top of the processor die instead of inside it. They envision 4 stackes of 256MB cache on top of the processor for a total of 1GB of cache.

Things are getting really interesting in the CPU market. I am hoping that AMD will come out with something totally new to keep the competition at a peak.

Competition is good for us consumers.
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#3
Zalmann
by: Kreij
I am hoping that AMD will come out with something totally new to keep the competition at a peak.
Well, the consumer market may be a little behind the server market, but I'm sure the technology will come to benefit consumers within the next few years.
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#4
Bastieeeh
Actually this technology is atm not targeted at stacking x86 CPUs on top of each other because the immense heat such chip bundles would generate can't be cooled away fast enough. This technology is aimed at smaller devices and therefore simpler chip designs like cell phones. I am a bit worried about the TPU! news post because it's misleading in several ways...
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#5
Jimmy 2004
by: Bastieeeh
Actually this technology is atm not targeted at stacking x86 CPUs on top of each other because the immense heat such chip bundles would generate can't be cooled away fast enough. This technology is aimed at smaller devices and therefore simpler chip designs like cell phones. I am a bit worried about the TPU! news post because it's misleading in several ways...
PM me where you think it's misleading - I'm basing it on the source, but there might be something that I didn't understand.

Edit: IBM is planning to use this in its servers and supercomputers, not just cellphone stuff:

http://www-03.ibm.com/press/us/en/pressrelease/21350.wss
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#6
lemonadesoda
No, the news post is still misleading:

by: from IBM site
3-D FOR WIRELESS COMMUNICATIONS TECHNOLOGY: IBM is using through-silicon via technology to improve power efficiency in silicon-germanium based wireless products up to 40 percent, which leads to longer battery life. The through-silicon via technology replaces the wire bonds that are less efficient at transferring signals off of the chip.

POWER PROCESSORS EXPLORE 3-D FOR POWER GRID STABILITY: As we increase the number of processor cores on chips, one of the limitations in performance is uniform power delivery to all parts of the chip. This technique puts the power closer to the cores and allows each core to have ample access to that power, increasing processor speed while reducing power consumption up to 20 percent.

BRINGING 3-D STACKING TO BLUE GENE SUPERCOMPUTING AND MEMORY ARRAYS: The most advanced version of 3-D chip stacking will allow high-performance chips to be stacked on top of each other, for example processor-on-processor or memory-on-processor. IBM is developing this advanced technology by converting the chip that currently powers the fastest computer in the world, the IBM Blue Gene supercomputer, into a 3-D stacked chip. IBM is also using 3-D technology to fundamentally change the way memory communicates with a microprocessor, by significantly enhancing the data flow between microprocessor and memory. This capability will enable a new generation of supercomputers. A prototype SRAM design using 3-D stacking technology is being fabricated in IBM's 300 mm production line using 65 nm- node technology.
There will not be "3D stacked processors" but rather, more effective "injection" of power lines within the processor, and improved interconnects between memory and processor.

Basically, for processors, the chip is NOT STACKED... but the connections are being made "into the chip" rather than just "at the edge" of the chip. For anyone who knows how silicon is designed, this is a breakthrough. Excellent.
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#7
Zalmann
by: Bastieeeh
Actually this technology is atm not targeted at stacking x86 CPUs on top of each other because the immense heat such chip bundles would generate can't be cooled away fast enough. This technology is aimed at smaller devices and therefore simpler chip designs like cell phones. I am a bit worried about the TPU! news post because it's misleading in several ways...
Well, I'm talking about server stuff, and not necessarily x86 based servers either. There are lots of non-WinTel based servers out there that is mainly what I am referring to.
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#8
Jimmy 2004
Ok, to clear up confusion on this story I've decided to change this story to a press release direct from IBM. For anyone interest, I've posted the old story below:

by: Jimmy 2004
IBM Working on CPU Stacking

IBM is working on an interesting new method of stacking CPUs with memory
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