| Monday, August 11th 2008 |
Chinese website Hardspell conducted a comprehensive pre-release evaluation of the upcoming Deneb 45nm Quad-core processor by AMD. The Deneb core incorporates thrice the amount of L3 Cache (that's 6 MB), and uses the same SIMD sets as its 65nm counterparts.
Here's a shocker: While the Phenom X4 9650 (65nm, 2.30 GHz, B3) consumes 104.1 W at load (peak), the 45nm Deneb (45nm, 2.30 GHz) peaks at an astonishing 57.3 W according to Hardspell's findings, go to see, the Deneb has an added load of transistors due to a 300% increase in the L3 Cache size. Let's bring in some numbers and figures.
CPU-Z Identification
Version 1.46.2 and above of CPU-Z detects the processor except the CPUID string which the engineering samples don't usually bring along. The 2.30 GHz Deneb Part comes with a 1.80 GHz HT link with 3600 MT/s of system bandwidth over the HyperTransport 3.0 bus. The L3 Cache uses 48-way set-associative paths.
Power Consumption
Specifications of the test-bed are provided. The 65nm Agena part was compared to the 45nm Deneb at the same clock-speed, idle and load consumptions were measured (first chart: idle, second: load):
Benchmark Scores
Fritz Chess (higher is better):
W-Prime Multithreaded Benchmark (time, lower is better):
POV-Ray 3.7 beta23 SSE2 (higher is better):
H.264 Encoding (time, lower is better):
3DMark Vantage (CPU score, higher is better):
The test bed was configured as follows:
Source: Hardspell
Here's a shocker: While the Phenom X4 9650 (65nm, 2.30 GHz, B3) consumes 104.1 W at load (peak), the 45nm Deneb (45nm, 2.30 GHz) peaks at an astonishing 57.3 W according to Hardspell's findings, go to see, the Deneb has an added load of transistors due to a 300% increase in the L3 Cache size. Let's bring in some numbers and figures.
CPU-Z Identification
Version 1.46.2 and above of CPU-Z detects the processor except the CPUID string which the engineering samples don't usually bring along. The 2.30 GHz Deneb Part comes with a 1.80 GHz HT link with 3600 MT/s of system bandwidth over the HyperTransport 3.0 bus. The L3 Cache uses 48-way set-associative paths.
Power Consumption
Specifications of the test-bed are provided. The 65nm Agena part was compared to the 45nm Deneb at the same clock-speed, idle and load consumptions were measured (first chart: idle, second: load):
Benchmark Scores
Fritz Chess (higher is better):
W-Prime Multithreaded Benchmark (time, lower is better):
POV-Ray 3.7 beta23 SSE2 (higher is better):
H.264 Encoding (time, lower is better):
3DMark Vantage (CPU score, higher is better):
The test bed was configured as follows:
Source: Hardspell
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