TSMC 16 NM Questions

[TheBrainyOne]

So I just came to know that TSMC 16 NM FinFET is launching next year. I was initially confused as to how TSMC was transitioning so quickly from 20 NM planar to 16 NM FinFET. Then I read that "16 NM FinFET" is actually 20 NM FinFET and TSMC is calling it 16 NM for some stupid reason.
So far it was easy albeit stupid.

Then I read that after 16 NM FinFET comes 16 NM FinFET Turbo/Plus and after that there will be an "even better" 16 NM FinFET. So now I am confused as to what the hell are these FinFET+ and "even better" FinFET things. Any help?

 

[Hilux SSRG]

Never trust TSMC and their product timelines, they change dates so often when being quoted in articles.

I would think the FinFET Turbo/Plus terms are some advancements to the 20nm process? Better efficiencies?

 

[BiggieShady]

The thing is the fins get narrower at the top so 20 nm wide fin at the base is 16 nm wide at the top ... it's great for marketing

 

[TheBrainyOne]

The thing is the fins get narrower at the top so 20 nm wide fin at the base is 16 nm wide at the top ... it's great for marketing

Does Intel does this too?? If not, any non-marketing related reasons for the trapezoidal design??

 

[BiggieShady]

Any non-marketing related reasons for the trapezoidal design??

There was a great deal of research to make production cheaper from intel's original design. Some variants of process give more rectangular fins and other trapezoidal fins ... marketing comes afterwards ... they are simply 'calling' the design 16 nm by measuring different areas from one transistor to the other.

 

[Devon68]

Well if you had brought up TSMC then read this:
http://www.game-debate.com/news/?ne...ia 20nm Maxwell GPUs Delayed Until Early 2015
short version:

Rumours are circulating that Nvidia has hit a snag with its 20nm Maxwell GPU production, because the Taiwan Semiconductor Manufacturing Company (TSMC) is not ready for the new process.

Sources at SweClockers are claiming that while the TSMC have begun producing the new GPUs, large scale production for the 20nm process, which could see the debut of Nvidia’s full Maxwell architecture range pushed back until late 2014 or even early 2015…

 

[TheBrainyOne]

There was a great deal of research to make production cheaper from intel's original design. Some variants of process give more rectangular fins and other trapezoidal fins ... marketing comes afterwards ... they are simply 'calling' the design 16 nm by measuring different areas from one transistor to the other.

Any ideas which variant of the design is better from performance/watt and performance/dollar perspective??

 

[TheBrainyOne]

which could see the debut of Nvidia’s full Maxwell architecture range pushed back until late 2014 or even early 2015…

Full Maxwell = GM110??

 

[64K]

Well if you had brought up TSMC then read this:
http://www.game-debate.com/news/?news=11999&graphics=GeForce GTX 750&title=Rumour: Nvidia 20nm Maxwell GPUs Delayed Until Early 2015
short version:

Rumours are circulating that Nvidia has hit a snag with its 20nm Maxwell GPU production, because the Taiwan Semiconductor Manufacturing Company (TSMC) is not ready for the new process.

Sources at SweClockers are claiming that while the TSMC have begun producing the new GPUs, large scale production for the 20nm process, which could see the debut of Nvidia’s full Maxwell architecture range pushed back until late 2014 or even early 2015…

I was reading an article earlier that said Nvidia has changed the road map. Unified memory is no longer going to be a feature for Maxwell but is being pushed back until 2016 with Pascal. Volta has been replaced my Pascal. We already know that with the 28 nm GPUs that Maxwell is going to be good with performance per watt so I expect that when the 20 nm GM110 finally does get to market and if they make it a 250 watt TDP then it should be quite powerful but it doesn't surprise me that they are having problems at 20 nm. TSMC had yield problems with Kepler at 28 nm at first too.

 

[BiggieShady]

Any ideas which variant of the design is better from performance/watt and performance/dollar perspective??

The leakage in the tapered fin is 17% lower than in the rectangular fin (source)
Less leakage means less power needed and better clocks are possible, so tapered fins are better for performance/watt.
As for performance/dollar, don't worry about that - they always manage to price the chips 'accordingly'

 

[TheBrainyOne]

The leakage in the tapered fin is 17% lower than in the rectangular fin (source)
Less leakage means less power needed and better clocks are possible, so tapered fins are better for performance/watt.

"The 15 nm wide rectangular fin has 24% higher on-current than for the tapered fin."

Doesn't this affect performance??

 

[TheBrainyOne]

Did a lot of googling. Found this:

"He added that back-end design rules would be similar to 16nm FinFET but that there would also be opportunities to use the Plus transistor to reduce standard cell size and therefore reduce chip size."

But I don't understand it. Help!!

Source: https://www.google.co.in/url?sa=t&s...XyyAjjIs58wujrfsQ&sig2=3_dyHl4ppu70z96X1006nw

 

[Steevo]

The whole point of smaller processes is smaller semiconductor wiring to reduce the capacitance of the material that is switching, meaning a faster roll off (voltage state change) and faster charge up with less voltage, also meaning less heat and higher clocks.

More transistors in a given area that can feed stability off a power point coming through the layers means less space spent on support structure and more on working parts.

The plus transistor is a unknown other than they may have been able to improve the switching, leakage, or other performance states of the silicon.

 

[BiggieShady]

Did a lot of googling. Found this: "He added that back-end design rules would be similar to 16nm FinFET but that there would also be opportunities to use the Plus transistor to reduce standard cell size and therefore reduce chip size." But I don't understand it. Help!!

They are talking about the SRAM cell size that consists out of 6 transistors :

With Fin-FETs one transistor can have multiple fins and also one fin can have multiple transistors. In the SRAM cell two transistors have 2 fins.
What you have read is that chip manufacturers don't have to move to a smaller node to reduce the cell size, they can change the fin configuration (have transistors with less fins or share fins between transistors) and the new 'plus' transistor allows just that (or so they claim).

 

[BiggieShady]

English isn't my native tongue. Please co-operate.

I tried

 

[TheBrainyOne]

I tried

Uh, sorry. Didn't read your post carefully.


I guess this thread should be closed now. I haven't studied enough (yet) to understand what all these technical terms mean, so there is no point in continuing this thread.

 

[micropage7]

its getting too technical
16nm like when moving from 40nm to 32nm, it offers lower power consumption and better performance
with moving to 16nm, you can put more transistors in the same area without risking it will eat much power and giving higher hear
but the smaller. the risk of broken transistor may higher too

 

[Steevo]

The risk of flaws in the silicon that will not allow operation of the deposited/etch layer is higher, flaws are the same size, but the fins get smaller and the flaw occludes more of them.

 

[Nanyast]

What is the difference between FinFET Turbo and FinFET Plus terms?

 

[Solaris17]

What is the difference between FinFET Turbo and FinFET Plus terms?

Finfet Turbo is supposed to be another branch off of the 16nm finfet but it is just a rumor right now.