d44ve
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- Apr 16, 2007
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| Processor | Intel E6600 @ 4.2GHZ Wo0t! |
|---|---|
| Motherboard | ASUS Striker Extreme & eVGA 680i A1 |
| Cooling | Phase Change !! |
| Memory | OCZ SLI 1066MHZ (2GB) |
| Video Card(s) | EVGA 8800 GTX |
| Storage | Western Digital 320 GB |
| Case | Antec 900 |
| Power Supply | Lian-Li V2000 |
| Software | Vista Ultimate |
Intel 4004
Introduced November 15-16, 1971
Clock speed 740 kHz
0.06 MIPS
Bus Width 4 bits (multiplexed address/data due to limited pins)
PMOS
Number of Transistors 2,300 at 10 µm
Addressable Memory 640 bytes
Program Memory 4 KiB
One of the earliest Commercial Microprocessors (cf. Four Phase Systems AL1, F14 CADC)
Originally designed to be used in Busicom calculator
Intel 8008
Introduced April 1, 1974
0.64 MIPS
Bus Width 8 bits data, 16 bits address
NMOS
Addressable memory 64 KiB
10X the performance of the 8008
Used in the Altair 8800, Traffic light controller, cruise missile
Required six support chips versus 20 for the 8008
Intel 8085
Introduced March 1976
Clock speed 5 MHz
0.37 MIPS
Bus Width 8 bits data, 16 bits address
Number of Transistors 6,500 at 3 µm
Assembly language downwards compatible with 8080.
Used in Toledo scale. Also was used as a computer peripheral controller - modems, harddisks, etc...
CMOS 80C85 in Mars Sojourner, Radio Shack Model 100 portable.
High level of integration, operating for the first time on a single 5 volt power supply, from 12 volts previously. Also featured two serial I/O connection,3 maskable interupts,1 Non-maskable,1 programmable,status,DMA.
Intel 8086
Introduced June 8, 1978
Clock speeds:
5 MHz with 0.33 MIPS
8 MHz with 0.66 MIPS
10 MHz with 0.75 MIPS
The memory is divided into odd and even banks. It accesses both the banks simultaneuosly in order to read 16 bit of data in one clock cycle.
Bus Width 16 bits data, 20 bits address
Number of Transistors 29,000 at 3 µm
Addressable memory 1 megabyte
10X the performance of 8080
Used in portable computing
Used segment registers to access more than 64 KiB of data at once, bane of programmers' existence for years to come
Intel 80286, the last 16-bit CPU
Introduced February 1, 1982
Clock speeds:
6 MHz with 0.9 MIPS
8 MHz, 10 MHz with 1.5 MIPS
12.5 MHz with 2.66 MIPS
16 MHZ, 20MHz and 25MHz available.
Bus Width 16 bits
Included memory protection hardware to support multitasking operating systems with per-process address space
Number of Transistors 134,000 at 1.5 µm
Addressable memory 16 mebibytes
Added protected-mode features to 8086 with essentially the same instruction set
3-6X the performance of the 8086
Widely used in PC clones at the time
Can scan the Encyclopædia Britannica in 45 seconds
Intel 80386, the first generation of Intel 32-bit CPU
Introduced October 17, 1985
Clock speeds:
16 MHz with 5 to 6 MIPS
20 MHz with 6 to 7 MIPS, introduced 16 February 1987
25 MHz with 8.5 MIPS, introduced 4 April 1988
33 MHz with 11.4 MIPS (9.4 SPECint92 on Compaq/i 16K L2), introduced 10 April 1989
Bus Width 32 bits
Number of Transistors 275,000 at 1 µm
Addressable memory 4 gibibytes
Virtual memory 64 tebibytes
First x86 chip to handle 32-bit data sets
Reworked and expanded memory protection support including paged virtual memory and virtual-86 mode, features required by Windows 95 and OS/2 Warp
Used in Desktop computing
Can address enough memory to manage an eight-page history of every person on earth
Can scan the Encyclopædia Britannica in 12.5 seconds
Intel 486
Introduced April 10, 1989
Clock speeds:
25 MHz with 20 MIPS (16.8 SPECint92, 7.40 SPECfp92)
33 MHz with 27 MIPS (22.4 SPECint92 on Micronics M4P 128 KiB L2), introduced 7 May 1990
50 MHz with 41 MIPS (33.4 SPECint92, 14.5 SPECfp92 on Compaq/50L 256 KiB L2), introduced 24 June 1991
Bus Width 32 bits
Number of Transistors 1.2 million at 1 µm; the 50 MHz was at 0.8 µm
Addressable memory 4 gibibytes
Virtual memory 1 tebibyte
Level 1 cache on chip
Math coprocessor on chip
50X performance of the 8088
Used in Desktop computing and servers
Family 4 model 3
Intel Pentium
Bus width 64 bits
System bus speed 60 or 66 MHz
Address bus 32 bits
Addressable Memory 4 gibibytes
Virtual Memory 64 tebibytes
Superscalar architecture brought 5X the performance of the 33 MHz 486DX processor
Runs on 5 volts
Used in desktops
16 KiB of L1 cache
P5 - 0.8 µm process technology
Intel Pentium Pro
Introduced November 1995
Intel Pentium MMX
Introduced January 8, 1997
Intel MMX instructions
Socket 7 296/321 pin PGA (pin grid array) package
32 KiB L1 cache
Number of transistors 4.5 million
System bus speed 66 MHz
Basic P55C is family 5 model 4, mobile are family 5 model 7 and 8
Intel Pentium II
Introduced May 7, 1997
Pentium Pro with MMX and improved 16-bit performance
242-pin Slot 1 (SEC) processor package
Number of transistors 7.5 million
32 KiB L1 cache
512 KiB ½ speed external L2 cache
The only Pentium II that did not have the cache at ½ speed of the core was the Pentium II 450 PE
Intel Celeron
Introduced April 15, 1998
242-pin Slot 1 SEPP (Single Edge Processor Package)
Number of transistors 7.5 million
66 MHz system bus speed
32 KiB L1 cache
No L2 cache
Intel Pentium III
Introduced February 26, 1999
Improved PII, i.e. P6-based core, now including Streaming SIMD Extensions (SSE)
Number of transistors 9.5 million
512 KiB ½ speed L2 External cache
242-pin Slot 1 SECC2 (Single Edge Contact cartridge 2) processor package
System Bus Speed 100 MHz, 133 MHz (B-models)
Family 6 model 7
Intel Coppermine
Introduced October 25, 1999
Number of transistors 28.1 million
256 KiB Advanced Transfer L2 Cache (Integrated)
242-pin Slot-1 SECC2 (Single Edge Contact cartridge 2) processor package, 370-pin FC-PGA (Flip-chip pin grid array) package
System Bus Speed 100 MHz (E-models), 133 MHz (EB models)
Family 6 model 8
Intel Pentium IV
Introduced November 20, 2000
L2 cache was 256 KiB Advanced Transfer Cache (Integrated)
Processor Package Style was PGA423, PGA478
System Bus Speed 400 MHz
SSE2 SIMD Extensions
Number of Transistors 42 million
Used in desktops and entry-level workstations
Intel Mobile Pentium II
Intel Mobile Celeron
Intel Mobile Pentium III
Intel Pentium II Xeon
Intel Pentium III Xeon
Introduced October 25, 1999
Number of transistors: 9.5 million at 0.25 µm or 28 million at 0.18 µm)
L2 cache is 256 KiB, 1 MiB, or 2 MiB Advanced Transfer Cache (Integrated)
Processor Package Style is Single Edge Contact Cartridge (S.E.C.C.2) or SC330
System Bus Speed 133 MHz (256 KiB L2 cache) or 100 MHz (1 - 2 MiB L2 cache)
System Bus Width 64 bit
Addressable memory 64 gibibytes
Used in two-way servers and workstations (256 KiB L2) or 4- and 8-way servers (1 - 2 MiB L2)
Family 6 model 10
Intel Xeon
Intel Itanium
Introduced 2001
more to come in a second
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nice work guys.
