Clowns are entertaining, but I don't turn to them for news.
Asses can carry a lot of weight, but I don't ask them for comments about other peoples "leaks" (NOT news).
May I kindly suggest that if you have nothing to give, then give nothing.
MLID "leaks" information, has discussions with insiders and formulates his own conclusions and then releases them to the public as HIS leaks and opinions. You could very easily do the same, if you are not able or willing to do so, then simply do not read or watch what he has to offer, and do not add your empty comments in places like this.
i wouldn't be surprised if they remove the L3 cache from the die and move it to a dedicated silicon with the 16 cores and 32 cores CCD. Like Denver said, Cache barely scale with newer process so if they want to keep a similar amount of cache per cores.
Another advantages of having a dedicated die for cache is they are able to squeeze more into the same area since you can use a different libraries.
The IPC gains aren't incredible, but they aren't that bad too. the key thing is the cadence they release, if they get it every 12-18 month, they should remain competitive.
Zen 6 is bringing a significant change in packaging, so something along these lines is not just possible, but expected. Intel is also working on something like this, it is codenamed "Adamantine" and was/is aimed to be a 128MB slab of some kind of Cache/RAM, not enough details have been leaked yet to know what this is exactly, but most likely to be L3 or L4 Cache, the question remains as to whether this was a realistic target, how well it works, how much it costs, especially in packaging, what the energy consumption is, will it have drawbacks (energy consumption for example).
That both Intel and AMD are working with advanced packaging techniques, 2.5 and 3D silicon, both active and inactive silicon layers, says a lot about where things are going as the physical, electrical and thermal problems mount as the lithographic processes become more difficult and expensive. The future of CPU's and other performance Silicon is going to end up with fully 3D chips for the performance, with the less performant silicon attached in the traditional manner, off to the side, and perhaps some distance away.
"Chips" have not had such dramatic and exciting changes for a long time, this alone is entertainment for us Geeks.
Not going to happen that segmentation of Desktop staying Dual channel, then workstation/pro 4 quad channel then server 8 channel will stay the same as that is done on purpose.
This will change in the not so distant future. AMD is building what some have named as a "Super APU", it has a quad channel memory design - for laptops / notebooks, and one assumes also for desktops.
As it is aimed at laptops, and for gaming, it makes sense to run quad channel RAM with a beefy amount of graphics power. Right now however we can only speculate as to the nature of the RAM, will it be GDDR6/X/7 soldered to the board right next to the APU, or will that be half of the RAM and the rest is DDR5, which would add an extra degree of complexity, or will it all be DDR5, if so will it be soldered down or will the laptops have 4x SODIMM slots.!?!? All unknown ATM, but this is a real planned product and will be using Zen 5 cores, so that gives a timescale.
As for Workstation CPU's, AMD has just announced a new socket for "mini EPYC" CPU's, they have up to 64 Zen 4c cores (standard Zen 4c chiplets, up to 4x16), and reuse the standard I/O die, but have fewer available PCIe lanes, and 6-channel RAM (rather than 12).
There is no reason why AMD could not use this socket for future Workstation CPU's, I would welcome that, and as always, there has been a great deal of speculation about this future potential use of the new SP6 socket.
Video linked below.
AMD "mini-EPYC" Sierra CPU and platform overview.