14th Gen Core desktop processors do not support Thunderbolt 5, even though Intel has their own TB5 controller design codenamed "Barlow Ridge". However, these won't arrive before Q1 2024, the currently shipping "Maple Ridge" controller has only support for Thunderbolt 4. But even once Barlow Ridge is available, they will not be compatible with "Raptor Lake Refresh" socketed desktop processors.
1. Discrete TB5 - desktop PC needs a source of DP 2.1 UHBR20 at 80 Gbps to be TB5 certified (unless Intel relaxes the process...)
- this is why current desktop CPUs cannot support TB5 - neither Intel nor AMD iGPUs provide DP 2.1 signal UHBR20
- iGPU on Intel desktop CPUs and their sister -HX SKUs on laptop do not support DP 2.1 at all, hence CPU cannot provide any UHBR signal
- iGPU on AMD desktop CPUs and their sister -HX SKUs on laptop do support DP 2.1, but only UHBR10 signal, so cannot be certified for TB5
- for a motherboard vendor to certify their boards with Intel as TB5 compliant, they need to bring UHBR20 signal at 80 Gbps into the system
- only AMD W7000 PRO GPUs provide the source of DP 2.1 80 Gbps signal that could be brought into Barlow Ridge chip via DP IN port
- that's why first TB5 ports could appear next year in HEDT or workstation systems that must use AMD W7000 PRO cards
- paradoxically, this could be all-AMD Threadripper system with W7000 PRO card or Intel's system with Sapphire R., Emerald R. or RPL E2400 CPU with the said GPUs.
- TB5 on desktop will be very niche and high-end solution for a few long years, until future iGPUs support DP 2.1 UHBR20 video signal on die and until AMD and Nvidia release next gen client GPUs with the said signal for motherboards with DP IN port.
2. Bandwidth Boost conundrum - DP is the King in Tx-mode, PCIe data is secondary
Thunderbolt is a complex bus, which combines a number of links besides PCIe, such as DisplayPort, which is how it arrives at its advertised bandwidth. So 80 Gbps is really just 64 Gbps of underlying PCIe bandwidth, and 120 Gbps is really just 96 Gbps
- without Bandwidth Boost, two NVMe Gen4 drives on both ends of TB5 cable should be able to use 64 Gbps in each direction, 128 in total
- with Bandwidth Boost, this cripples one NVMe Gen4 drive to half speed
- both of the above solutions can only work at the said speeds if there is no concurrent DP traffic saturating the remaining bandwidth on either 80 Gbps or 120 Gbps link
- Bandwidth Boost was primarily designed to benefit video data for displays; PCIe data traffic can only 'suffer' in this mode
The way we understand Thunderbolt 5 Bandwidth Boost to work, for the ability to push 120 Gbps through a PCI-Express 4.0 x4 connection between the "Barlow Ridge" controller and the processor's PCIe root complex, the root complex should be able to re-task both sub-lanes of two of the four PCIe lanes for either purely-Tx or purely-Rx.
- it's more complicated, as we have downstream and upstream ports too, in addition to Tx and Rx traffic
- Intel showed on their slides that 120 Gbps link works only in Tx mode, so the feature will not work in Rx mode on downstream port (the one on the motherboard)
- this makes sense, as the feature is predominantly for DP data for more advanced displays
- the feature will work in Rx mode on upstream port only (the one on the hub or in a display, for example)
With Bandwidth Boost enabled, three out of four links are loaded toward one direction to make 120 Gbps, while the last link is in the opposite direction. As for which direction gets the Bandwidth Boost depends entirely on the application, as detailed in the examples above. You get get a 120 Gbps high-speed transmit with a 40 Gbps receive, or a 120 Gbps high-speed receive with a 40 Gbps transmit. The second image drawn by us, illustrates how the PCIe backend works between the Thunderbolt 5 host controller and the PCIe root complex.
- yes, your diagram makes sense
- as said above, the direction of Bandwidth Boost is Tx on downstream port and Rx on upstream port; this is due to DP traffic priority
for Thunderbolt 5 to be able to push 120 Gbps to a downstream device, there needs to be a PCIe Gen 4 x8 connection between the PCIe root and the "Barlow Ridge" host controller that can provide 160 Gbps of per-direction bandwidth, which is both undesirable and unlikely, as all prior generation discrete Thunderbolt controllers by Intel have used a PCIe x4 connection to the platform.
- triggering 120 Gbps link will depend on DP signal need. PCIe is secondary.
- Intel needs to clarify the moment when 120 Gbps link kicks in. It seems to me that such moment is triggered when the controller senses that video traffic needs more than 80 Gbps, for example:
- two monitors with UHBR13.5 signal that require 108 Gbps
- three monitors with UHB10 signal that require 120 Gbps
- one UBR20 and one UHBR10 monitor
- It does look like that these combinations are baked into DP protocol identifier on Barlow Ridge and managed by software.
- it's not clear how DSC would behave. It could trigger automatically once 120 Gbps are exhausted for uncompressed DP traffic
- this means that PCIe traffic could completely stop in edge scenarios when DP data takes all available bandwidth. Intel needs to clarify whether there is any minimally reserved bandwidth for PCIe traffic. There should be some, because I cannot imagine the situation when 80 or 120 Gbps are saturated with DP only and my storage peripherals cannot receive any PCIe data from PC.
It's very likely that these "Raptor Lake Refresh-H/HX" processors are the ones that support Thunderbolt 5 from the 14th Gen using "Barlow Ridge" controllers, besides the upcoming "Meteor Lake" processors that have "Thunderbolt 5" integrated as part of its SoC tile.
3. Integrated TB5 in mobile SKUs
- Meteor Lake does not have integrated TB5. Intel confirmed that TB4 is integrated on I/O tile, up to four ports
- bizarelly, Meteor Lake does have, on Intel's slides, DP 2.1 with support for UHBR20 signal ('20G'), so this CPU is not ready for TB5 for other reasons that Intel has not disclosed
- the first mobile CPUs that could integrate TB5 on I/O tile could be Arrow Lake-H, so we are looking into ~CES 2025, but I would not be surprised if they leave it for Lunar Lake because they launched TB3 and TB4 on low-power mobility CPUs Ice Lake and Tiger Lake.
- I am curious about Gigabyte showcase laptop with RPL-HX that Intel used to present discrete TB5 solution during Innovation event
- where did they take DP 2.1 80 Gbps signal from to feed Barlow Ridge controller with?
- did they upgrade DP on Raptor Lake iGPU?
- or did they use specially prepared mobile GPU to source the signal, such as custom A770M or unreleased AMD W7000M? Curious case.
Intel rushing "14th gen" so hard that they're dropping worthwhile features left right and centre. Plus we're going to be in a nightmare scenario whereby some "14th gen" processors support TB5 and some don't, so consumers will be horribly confused.
No. There will be one or two halo laptops that would premier TB5 for the sake of existence in the market. TB5 will not become widespread any time soon. It will be a high-end, premium feature for a few years.
seems to be pretty stable
It was supposed to become more widespread than ever once Intel decided to donate the spec to USB-IF.
In many reviews the lack of TB support is described as a (big) disadvantage for AMD based laptops. Even if it's real significance is limited, it is used in marketing.
It's enough if AMD laptop has USB4 port, which usually has the same features. I have one at home with 40 Gbps.
Also, the asynchronous transfer mode will most likely just be for DP signals anyhow.
This.
Keep in mind that Thunderbolt maxes out at USB 3.2 Gen 2 10 Gbps speeds, yet Intel forced a 20 Gbps mode for the USB4 spec that no-one really wanted.
USB 10 Gbps (xHCI 1.1 controller) is a minimum requirement for TB5, however Intel is introducing USB 20 Gbps too, with xHCI 1.2 controller.
Why not just use a pcie5.0x4 root complex? The usb4v2 spec has a revision to specifically allow for pcie5.0. Seems like that would’ve been easier and cleaner to allow for up to 128 Gbps bandwidth.
from section 11.2 (Version 2.0 with Errata and ECN through June 29, 2023)
“An Internal PCIe Port shall be compatible with the PCI Express® Base Specification, Revision 4. An Internal PCIe Port may be compatible with the PCI Express® Base Specification, Revision 5.0.
Each data lane on TB5 is 20 Gbps, so PCIe Gen5 at 32 Gbps per lane would not fit.
