Originally Posted by kwchang007
How would you get 8 signals per clock cycle? Like DDR runs at the max and min I believe, QDR would be max, min + x intercepts? And ODR would be well i have no clue...
DDR3(PC3) uses 4 muxed signals per cycle to transmit 8 bits and next to promised ddr4 will use 8 muxed signals. But rambus is not ODR or HDR cause they are not 4 or 8 times phase shifted like ViA's ex-initaitive QDR that has 2+2 phase shifted signals. it's in fact just like that old QDR just with insane chopping CR up to 500MHz. While DDR3 for now is just @312,5MHz only (ddr3-2500: http://hothardware.com/News/Elpida-Develops-50nm-DDR3-SDRAM/)