[TheLostSwede]

No, that's how USB used to work, you see, there are two kinds of USB host controllers, UHCI/OHCI and EHCI of which the latter offer full bandwidth to pair of ports and this is how USB 3.0 is designed. With UHCI the bandwidth is shared between all ports in the system, which is a crappy solution. AMD's 800-series of southbridges features no less than three EHCI controllers which allows for six ports of near enough full speed bandwidth. USB 3.0 also uses EHCI as otherwise you'd get crap performance. So no, it's not how USB works any more.

This is also the standard that Intel controls, also referred to as xHCI and this is what Intel doesn't want to move from revision 0.9x to 1.0 as then Intel would have to implement USB 3.0 into its chipsets.

As such you need a lot more bandwidth available per pair of USB 3.0 ports than you claim, in fact, each EHCI pair requires the full 5Gbps worth of bandwidth. This is also why it's so hard to implement USB 3.0, not counting the physical board implementation, as a single lane of PCI Express gen 1 bandwidth isn't enough. As I said, I very much doubt we'll see more ports, although four shouldn't really be a problem for AMD, especially as Renesas and TI are already working on solutions for this and VIA allegedly has a solution ready...

Forgot to say that USB 3.0 also has much better data routing than USB 2.0, as in it's more like a smart switch than a dumb hub in terms of getting the right bits to the right place as fast as possible.