Originally Posted by lemonadesoda
IMO cache should be refered to as 4 x 2MB, since NO single core (or thread) has access to more than 2MB.
While the intel solution is clever at scaling, it is incredibly inefficient. If you have an application, e.g. Photoshop, running 4 threads or a filter, then each of the 2MB cache has, essentially, the same data.
Any other cache design would make the cache and memory controller very complex and may add additional latency... and I understand why Intel chose the existing solution... but we should definitely not refer to 8MB cache, but 4 x 2MB.
im not saying your wrong about this but where did you get the information that "NO single core (or thread) has access to more than 2MB cache" ? i just havent seen the same data myself
and what would be the point in putting redundant ram on a chip ? im sure enough techies would know that 2mb is the limit of cache on a chip and surely that would be made common knowledge