[erocker]

Originally Posted by bear jesus

I was under the impression the low end parts would still be VLIW4 and the high end would be the new compute architecture, although i don't think anything has been confirmed by AMD.

I've seen this posted at other sites, but I found the info below here: http://videocardz.com/28922/radeon-h...cture-detailed

VLIW4 to SIMD – This change allows for better GPGPU performance. VLIW5 and VLIW4 were efficient for graphics calculations, but not for general purpose (varying) CPU computations. SIMD brings the best of both worlds. In fact, Nvidia has been using this for quite some time within their Fermi architecture.

Unified Memory – Both CPU and GPU can utilize the same address spaces. The GPU now has built in address translation hardware just for this specific design implementation.

Improved C++ GPGPU programming and debugging support – Previously developers had to utilize assembly and some C to achieve the desired implementation. Now programmers can take full advantage of a high level language with AMD GPUs.

Compute Units – Instead of the traditional steam processor, AMD will utilized its new SIMD architecute (which is comprised of multiple ALUs making up a 16 bit wide vector SIMD block). Each compute unit has 4 SIMD blocks with an L1 cache. Overall, each CU with have its own L1 cache and all CU’s will share a L2 cache (which all Nvidia and AMD GPU’s currently employ).

Partially Resident Textures (PRT) – As with John Carmack’s MegaTexture technology, textures can now be partially loaded in memory for quicker access. This allows for the use of larger textures to be more efficiently used on a much larger scale than previous implementations. The main differnece is of course that insead of being implemented via software (id tech 5) it will now be implemented via hardware.