Originally Posted by [H]@RD5TUFF
And it will still be an underpowered lump of garbage.
It depends on how they implement the extra logical threads, we're not talking Bulldozer here. It's a completely different architecture running on a completely different processing paradigm.
I think everyone needs to stop comparing this to standard desktop CPUs unless you happen to be running a RISC processor on your tower, which I seriously doubt.
Basically it works like this.
Reasons for RISC:
Small, heavily optimized instruction set executable in single short cycle
All instructions same size
No microcode = faster execution
Extra speed more than offsets increased code size, reduced functionality
Better compiler target
Reasons for CISC:
Fewer instructions per task
Hardware implementation of complex instructions faster than software
Extra addressing modes help compiler
for lists since I'm lazy.