AMD to Sample Bulldozer Architecture in 2010, Sets Product Priorities

[wolf]

Originally Posted by crazy pyro

What the HELL type of parties do you go to Wolf?

Only the best ones

[PP Mguire]

Do want awesome parties.

[pantherx12]

If they were the best parties everyone would still be up by 4 in the morning!

That's when I used to go home from clubs and then party on boats until 9 am or so <_<

[wolf]

Originally Posted by pantherx12

If they were the best parties everyone would still be up by 4 in the morning!

That's when I used to go home from clubs and then party on boats until 9 am or so <_<

Depends how early you start and I always love a party cool enough for someone to get taped to the roof

seriously I'm sidetracking badly here. sorry bta

[PP Mguire]

I doubt bulldozer will be good enough to tear me away from my i5.

[eidairaman1]

Originally Posted by TheLaughingMan

Not me because I don't know what a cylon is.

Battlestar Galactica (Ended)

[TheMailMan78]

Originally Posted by eidairaman1

Battlestar Galactica (Ended)

When I was a kid the only thing cooler looking than a Cylon were the tie fighter pilots.

[Kantastic]

If this is new architecture from the ground up, I'd like to see it give Intel's HyperThreading a run for it's money. (Or pocket change.)

[eidairaman1]

Whats amazing is that is where the F-16 got its Nickname from, Pilots called it the Viper. Yet is the F-16: Fighting Falcon.

[Hayder_Master]

wow plan to 12 cores cpu for servers

[mandis]

I've learned not to expect much from amd these days.

I still think that amd's chips are of better quality and live longer than anything else on the market but this seems to be their only selling point these days...

[TheLaughingMan]

Originally Posted by mandis

I've learned not to expect much from amd these days.

I still think that amd's chips are of better quality and live longer than anything else on the market but this seems to be their only selling point these days...

And them being nice enough to ensure upgrade paths are simple and cheap. And their price/performance ratio.

I love how everyone just writes AMD off like the bastard, red-headed, step-child because they don't hold the absolute top spot in the performance charts.

Yes, Intel makes the fastest chips. Yes the i7 architecture is far ahead of AMD (except for games). But the K10 series and current stock of AM3 processors are leaps and bounds above the old Phenoms. Your 9950 even OC'ed to 3.2 is still handicapped compared to the Phenom II's. AMD is doing what they can do, improve their products with the resources available to them. Intel's R&D budget is probably higher than AMD entire corporate finance budget.

[vagxtr]

Originally Posted by Imsochobo

Phenom is basicly:
Improved HT
Improved Memory controller(added one aswell ) its dual 64 bit. not a single 128 bit if i got that right, something strange nonetheless.
Native Quadcore.
Improved IPC.
Support for Level 3 cache.
Over a A64 arch.

Maybe we'll see a New AMD juggernaut cpu from AMD, just like K7 K8 was

None of K8 architecture doesn't support HT (as Hyper Threading), and K8L or so called K10(.5) already get improved controller but AMD didnt resolve issues like broken half multi compatibility since K8 intro to first G1 late in 2006 (that's 3 fully years) and they build/test on that future of Phenom CPUs, and then they unganged memory so it could be accessed almost twice as faster with keeping latencies low like in real 128bit mode but that came at price when no easy OCing is possible since Phenom introduction cause no longer easy (for many claimed broken) CPU divider is used for memory frequency but now we have FSB multis like 1/2, 3/5 .... which makes memory always run at max even in PowerNow mode active. Well with detached MC with their own voltage control that doesnt have any affect except extra memory and mch consumption when CPU running in power saving mode and not really needing all of that memory bandwidth. They needed to implement PN for MCH too

IPC isn't much improved in Phenoms (K8L) over old Athlon64 they just get capability to crunch whole 128b SSE in one cycle and got ability to handle much larger pages (needed for server application where lies amd 95% design orientation since K8 introduction) and that's pretty much it. L3 came as quick solution for never developed unified L2 like Intel did in their Core 2 architecture and looking forward to what Intels Nehalems would look like all in one development and cutting r&d budget they never had. And as far as ipc improvement goes more of them was done by ViA in latest Isaiah iteration than AMD has done for it's ipc in the last three years well maybe even 4 after they implemented SSE3 in E3 Venice core

Bulldozer came out from realK10 development which is scraped down somewhere in 2006 and K9 was scraped year or two earlier. So they in fact look what IBM want for their server needs and looking on Sun's Niagara with already some job done in K10. What they really did in K9/K10 was never disclosed. Maybe that memory unganging came from one of that devs. Anyway K10 since it's first glimpses should have been a wholly revamped architecture, as Bulldozer should be, with only virtual support for old x86. And Bulldozer has that x86 nativlly implemented? Anyway HT in bd should resemble MHT like in Niagara (hence all that river codenames in amds bulldozer based server cpus ) not some QuasiSMT like Intel didi in past and latest Atom/Nealem iterations. Again feature needed for server market in architecture that should serve them for next 10 years??? As K7-K8-K8L redesign did.

[btarunr]

No, by HT he meant HyperTransport. Which indeed improved between K8 and K10. K10 used HyperTransport 3.0, with speeds between 1800 MHz (3.6 GT/s) and 2000 MHz (4.0 GT/s).

HyperThreading Technology is abbreviated as HTT.

[MrMilli]

Originally Posted by vagxtr

None of K8 architecture doesn't support HT (as Hyper Threading), and K8L or so called K10(.5) already get improved controller but AMD didnt resolve issues like broken half multi compatibility since K8 intro to first G1 late in 2006 (that's 3 fully years) and they build/test on that future of Phenom CPUs, and then they unganged memory so it could be accessed almost twice as faster with keeping latencies low like in real 128bit mode but that came at price when no easy OCing is possible since Phenom introduction cause no longer easy (for many claimed broken) CPU divider is used for memory frequency but now we have FSB multis like 1/2, 3/5 .... which makes memory always run at max even in PowerNow mode active. Well with detached MC with their own voltage control that doesnt have any affect except extra memory and mch consumption when CPU running in power saving mode and not really needing all of that memory bandwidth. They needed to implement PN for MCH too

IPC isn't much improved in Phenoms (K8L) over old Athlon64 they just get capability to crunch whole 128b SSE in one cycle and got ability to handle much larger pages (needed for server application where lies amd 95% design orientation since K8 introduction) and that's pretty much it. L3 came as quick solution for never developed unified L2 like Intel did in their Core 2 architecture and looking forward to what Intels Nehalems would look like all in one development and cutting r&d budget they never had. And as far as ipc improvement goes more of them was done by ViA in latest Isaiah iteration than AMD has done for it's ipc in the last three years well maybe even 4 after they implemented SSE3 in E3 Venice core

Bulldozer came out from realK10 development which is scraped down somewhere in 2006 and K9 was scraped year or two earlier. So they in fact look what IBM want for their server needs and looking on Sun's Niagara with already some job done in K10. What they really did in K9/K10 was never disclosed. Maybe that memory unganging came from one of that devs. Anyway K10 since it's first glimpses should have been a wholly revamped architecture, as Bulldozer should be, with only virtual support for old x86. And Bulldozer has that x86 nativlly implemented? Anyway HT in bd should resemble MHT like in Niagara (hence all that river codenames in amds bulldozer based server cpus ) not some QuasiSMT like Intel didi in past and latest Atom/Nealem iterations. Again feature needed for server market in architecture that should serve them for next 10 years??? As K7-K8-K8L redesign did.

Biggest load of crap i've seen for a while ....

[vagxtr]

Originally Posted by btarunr

No, by HT he meant HyperTransport. Which indeed improved between K8 and K10. K10 used HyperTransport 3.0, with speeds between 1800 MHz (3.6 GT/s) and 2000 MHz (4.0 GT/s).

HyperThreading Technology is abbreviated as HTT.

Well Hyper Threading was first one using abb. HT Just afterwards knowledge public asked for intel to differentiate themselves and in fact coining new abb HTT.

But what was i gonna ask is that on most places on the net we saw 2000MHz for HT3.0 (and 1000MHz for HT2.0 for the sake of reference) and adding to that as 4.0MT/s (and 2.0MT/s respectively). And thus gaining full bandwidth of 16GB/s (even in some official blogs. While most of more insight people use only 2.0MT/s x4bytes (2x 16bit lines) for HT3.0.

So i'd say i stand confused cause i know many of net advertisers use 2.0MT in HT2.0 just for the sake of marketing deliberately misleading people while it was just 1MT+1MT x16 bit or simply 1MT x2 x16bit and not in fact 2.0MT/s (reffering for HT2.0). So if you could clear out that misconceptions, especially in full XXGB/s bandwith in case of HT2.0 and now HT3.0.

Originally Posted by MrMilli

Biggest load of crap i've seen for a while ....

Could you been more thorough and wash your hands before typing.

[Super XP]

Originally Posted by MrMilli

Bulldozer has been in development from before 2007 (my guess is even before 2006)!
While i don't know the exact date that AMD commenced work on Bulldozer, designing a CPU architecture from the ground up generally takes 5 to 6 years (add a year sampling to that).
It has been confirmed already that Bulldozer is a completely new design developed from the ground up.

You mean before 2004. I would say more like 2003 about the same time Intel was working Sandybridge.

[[I.R.A]_FBi]

whats sandybridge

[OneCool]

Will they ever have a work around for Intels Hyper Threading?

That seems to be their big draw back ATM.

[PP Mguire]

Yea, its called bringing back pure AMD power. They have gotten used to being known as 2nd best again. I hate that.

[TIGR]

Ah bummer, I was hoping Bobcat was a GPGPU, but sounds like it's just AMD's equivalent to the i3s with integrated graphics. After Larrabee, wouldn't it be something to see AMD be the first to release a mainstream GPGPU?

And with ATI and all their work on OpenCL, why not?

[PP Mguire]

Actually, itd be the replacement of the i5 661+.

[Melvis]

Let the games begin

[nt300]

Originally Posted by [I.R.A]_FBi

whats sandybridge

It's Intels upcoming cpu design to compere with bulldozer.

Originally Posted by Melvis

Let the games begin

Theres a reason why AMD choose Bulldozer for its upcoming core design I think they plan on Bulldozing a bigger CPU company in 2011

[Melvis]

Originally Posted by nt300

Theres a reason why AMD choose Bulldozer for its upcoming core design I think they plan on Bulldozing a bigger CPU company in 2011

Yea they have been wanting to do this for awhile now. Ive been following it as much as i can since they first said about Bulldozer, just hope it does as well as they say it will do.