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Old May 4, 2011, 04:30 PM   #101
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Not with 2x16 & ddr3, i think

In AM3+ platform 990 chipset will provide full 16X+16X or 3X16 solution with no extra chips needed. No LATENCY with intermedially chips (NF200) . Native crossfire & native sli !
Some members here at TPU have this mobo, including myself; it does 2x16 lanes and support DDR3. I get similar results to X58 SLI systems on 3DMARK Vantage and 11 on extreme settings, obviously not on the performance setting which is cpu demanding. http://www.techpowerup.com/forums/sh...d.php?t=120367
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Old May 4, 2011, 04:38 PM   #102
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Some members here at TPU have this mobo, including myself; it does 2x16 lanes and support DDR3. I get similar results to X58 SLI systems on 3DMARK Vantage and 11 on extreme settings, obviously not on the performance setting which is cpu demanding. http://www.techpowerup.com/forums/sh...d.php?t=120367
claylomax.. i use to have this mobo bro.. but I changed it to Asus Crosshair 4 formula...
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Old May 4, 2011, 04:42 PM   #103
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Some members here at TPU have this mobo, including myself; it does 2x16 lanes and support DDR3. I get similar results to X58 SLI systems on 3DMARK Vantage and 11 on extreme settings, obviously not on the performance setting which is cpu demanding. http://www.techpowerup.com/forums/sh...d.php?t=120367
Unlock PHENOM II X2 555 !!!! 4,5Ghz and northbridge freq. 3300Mhz ???
what cooling system ??
Very very nice with budget cpu !

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In AM3+ platform 990 chipset will provide full 16X+16X or 3X16 solution with no extra chips needed. No LATENCY with intermedially chips (NF200) . Native crossfire & native sli !
I compare AM3+ with 1155 !

Nvidia does not make any AM3+ mobo & chip ...
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Old May 4, 2011, 04:47 PM   #104
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I compare AM3+ with 1155 !
Which is why AMD is so screwed because it will not be able to compete against the LGA2011 later this year.
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Nvidia does not make any AM3+ mobo & chip ...
With new deal, they don't need to, and they can focus on Tegra or whatever.
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Old May 4, 2011, 04:49 PM   #105
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@charts

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Old May 4, 2011, 04:56 PM   #106
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claylomax.. i use to have this mobo bro.. but I changed it to Asus Crosshair 4 formula...
I copy your post to include the link, I feel lazy ...
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Old May 4, 2011, 04:59 PM   #107
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Unlock PHENOM II X2 555 !!!! 4,5Ghz and northbridge freq. 3300Mhz ???
what cooling system ??
Very very nice with budget cpu !



I compare AM3+ with 1155 !

Nvidia does not make any AM3+ mobo & chip ...
Dumo probably used some kind of extreme cooling for that. Here's another link: http://www.xtremesystems.org/forums/...d.php?t=249897 EDIT: he used single stage.
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Old May 4, 2011, 05:11 PM   #108
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Even when you consider the 100MHZ increase in clockspeed and an extra 4 threads the Core i7 2600K is under 10% faster than a Core i5 2500K in PCMark Vantage:

http://www.neoseeker.com/Articles/Ha...5_2500K/8.html
Yeah, that's kind of what I was getting at about PCMark. Wait for other benches!

As for those who think the Bulldozer module is closer to hyperthreading than to two cores, think about what task the Interlagos processor (from which Zambezi is designed from) was designed for. In the server space, Integer performance is more valuable than floating point performance, and while the module may only have one fetch/decode unit, it has two integer execution units. Further, each has their own L1 Data cache, and the L2 cache is able to be dynamically divided amongst the cores in a module (even unfairly). As such, for integer processing, it performs about as well as two cores without any components shared.

As for floating point, there may be only one FPU, but with each cycle, either core can operate on 256 bits of parallel data via two 128-bit instructions or one 256-bit instruction, OR each of the integer cores can execute 128-bit commands simultaneously. This is actually an advantage over Sandy Bridge, as while Sandy Bridge may also support 256bit AVX instructions, should a program not be programmed to take advantage of those, it is limited to a single 128bit FPU. Further, bear in mind that a 256bit FPU takes up a huge amount of die space, and so sharing it is an important way of saving chip real estate (put it towards the massive L3 cache these chips will have).

AMD "averages" their module design performance by saying that if both cores in a module are active, you'll get around 80% the throughput performance of having two separate cores without any shared resources, but at a significantly lower amount of power consumption. On the other hand, looking at Intel's Hyperthreading, you're lucky to get more than 15% throughput increases on an out-of-order execution processor, but still with a noticeable increase in power consumption. Hyperthreading is much more beneficial on in-order execution processors like the Atom or the Xbox 360s PowerPC CPU, as the pipeline is stalled significantly more often.

For Zambezi at the desktop, one also has to take into consideration how the power saving settings are in the OS (likely configurable by an Administrator). Say a Bulldozer's cores are set up like this (grouped in twos):

12|34|56|78

One can choose from a maximum power saving profile, or a maximum performance profile. Let's say we are executing a program that takes advantage of a quad core, and no additional cores (like many games). If we're interested in maximum power saving, we'd see these cores activated:

12|34

On the other hand, if we're more interested in performance, we'd see this:

1|3|5|7

In the latter case, no resources would be shared (other than L3), and we'd have each individual core running with a full 2MB L2 cache and complete access to the FPU. As most games don't take advantage of more than 4 cores, and because we are enthusiasts here, we'll probably select that option. But others (especially mobile users) will likely opt for the first.
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Old May 4, 2011, 05:37 PM   #109
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This is actually an advantage over Sandy Bridge, as while Sandy Bridge may also support 256bit AVX instructions, should a program not be programmed to take advantage of those, it is limited to a single 128bit FPU
I didnt knew that about sandy . Thanks


Quote:
For Zambezi at the desktop, one also has to take into consideration how the power saving settings are in the OS (likely configurable by an Administrator). Say a Bulldozer's cores are set up like this (grouped in twos):

12|34|56|78

One can choose from a maximum power saving profile, or a maximum performance profile. Let's say we are executing a program that takes advantage of a quad core, and no additional cores (like many games). If we're interested in maximum power saving, we'd see these cores activated:

12|34 (each with 1mb l2 cache)

On the other hand, if we're more interested in performance, we'd see this:

1|3|5|7 (each with 2mb l2 cache)
Can we program that or Windows doing accidentally ? Ιf windows change that in application (plan a, plan b), did we have delay ?

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Old May 4, 2011, 05:48 PM   #110
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Can we program that or Windows doing accidentally ?
It will likely be a windows power setting, or some AMD driver one has to install. As for

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12|34 (each with 1mb l2 cache)
I never said that. The L2 cache is dynamically allocated to a core depending on its needs at the time. If it only needs 512k, then it'll be split .5MB/1.5MB. If it needs more, it'll request more, and either be denied or approved. Really cool, huh?
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Old May 4, 2011, 05:51 PM   #111
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i dont know, maybe this will help

http://www.techpowerup.com/img/11-01-24/177a.jpg

just look at X6 1100T, compare it to graph on the first post then you'll notice something different. or maybe absurd..
This chart is a load of shiste, they compare the x6 to a 950, which is socket 1366, then in the feature comparison compare it to a socket 1156 which is a truelly dead socket, AMD can't even inflate it's own numbers without failing.
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Old May 4, 2011, 05:56 PM   #112
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I never said that. The L2 cache is dynamically allocated to a core depending on its needs at the time. If it only needs 512k, then it'll be split .5MB/1.5MB. If it needs more, it'll request more, and either be denied or approved. Really cool, huh?
Yes I understand is dynamically. But if windows change from plan A to plan B in application, ,because cores want bigger cache, did we have delay ?

Plan A (12l34)

Plan B (1l3l5l7)
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Old May 4, 2011, 05:59 PM   #113
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This chart is a load of shiste, they compare the x6 to a 950, which is socket 1366, then in the feature comparison compare it to a socket 1156 which is a truelly dead socket, AMD can't even inflate it's own numbers without failing.
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Old May 4, 2011, 06:04 PM   #114
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Did I catch a nerv?

The reality is this I personally believe the chart is a well done troll rather than a leaked internal presentation slide, I personally want AMD to succeed so we can get a price war going, but it's hard to believe that AMD has to power to change their tune and go from the red headed step child to the favorite son (see what I did there). On the other hand I kinda want to see AMD fail so all the fanboy trolls can cry and be butt hurt, but cheaper chips trumps the pleasure of fanboy tears.
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Old May 4, 2011, 06:06 PM   #115
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Did I catch a nerv?

The reality is this I personally believe the chart is a well done troll rather than a leaked internal presentation slide, I personally want AMD to succeed so we can get a price war going, but it's hard to believe that AMD has to power to change their tune and go from the red headed step child to the favorite son (see what I did there). On the other hand I kinda want to see AMD fail so all the fanboy trolls can cry and be butt hurt, but cheaper chips trumps the pleasure of fanboy tears.
Whatever you gotta tell yourself.
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Old May 4, 2011, 06:11 PM   #116
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Whatever you gotta tell yourself.

Awwww QQ ?



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Old May 4, 2011, 06:14 PM   #117
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Yes I understand is dynamically. But if windows change from plan A to plan B in application, ,because cores want bigger cache, did we have delay ?

Plan A (12l34)

Plan B (1l3l5l7)
I haven't been told those kinds of specifics yet. I doubt Windows itself would just change power plans without manual intervention, so I don't see that happening. As for delays when changing cache size, there might be a couple special AMD instructions that execute to do that, but I doubt it'd be more than that. No human noticeable delay...

I also have little idea how the module determines how much L2 to allocate per core. If I had to guess, I'd say something like how a mutable array (like an ArrayList) manages it's back bone array data structure, where if it gets full past a certain threshold, then it requests more. Alternatively, if it is empty past a threshold, it reorganizes, and frees space. Just a guess.
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Old May 4, 2011, 10:32 PM   #118
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That your GF?????

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Old May 4, 2011, 10:43 PM   #119
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That your GF?????

Nope it's a self portrait . . . see you can clearly see the camera in my hand . . .
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Old May 5, 2011, 03:34 AM   #120
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This chart is a load of shiste, they compare the x6 to a 950, which is socket 1366, then in the feature comparison compare it to a socket 1156 which is a truelly dead socket, AMD can't even inflate it's own numbers without failing.
so did i believe the graph? no.. i'm just showing for what TPU had posted before.

like everybody said, i'll wait for the *real* benchs..
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Old May 5, 2011, 05:29 AM   #121
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If I understand this right the 8 core Bulldozer is on par with the 4 core 2600k. The only reason the P score is higher is it was tested with the 6670 GPU? Or am I reading this wrong.... valid question not trying to guess I really think I am reading this wrong? Or am I ???
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Old May 5, 2011, 01:45 PM   #122
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If I understand this right the 8 core Bulldozer is on par with the 4 core 2600k. The only reason the P score is higher is it was tested with the 6670 GPU? Or am I reading this wrong.... valid question not trying to guess I really think I am reading this wrong? Or am I ???
what i'm guessing it is for krisna which will have 8 "bulldozer cores" and 6670 or something like that.
But I have no clue if that's how it is or not, if its a non apu bulldozer with dedicated graphics then its bye bye amd...
But I sincerely hope not.
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Old May 6, 2011, 06:17 PM   #123
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If I understand this right the 8 core Bulldozer is on par with the 4 core 2600k. The only reason the P score is higher is it was tested with the 6670 GPU? Or am I reading this wrong.... valid question not trying to guess I really think I am reading this wrong? Or am I ???
You are not reading it wrong. It takes AMD 8 cores to be equal to Intel's 4 - something AMD should be embarrassed of publishing.

The 6670 GPU is part of AMD's Vision/Fusion APU where the CPU and GPU are integrated like with Intel's HD graphics.

AMD's graphics are obviously going to be stronger than Intel's HD graphics so therefore AMD's the P score is higher.

As far as value goes, AMD wins if the 8 core pricing is right because the CPU is on par with the 2600k but the graphics is MUCH better - so a better value over Intel's offering....especially if the 6670 GPU is better than what GPU the customer currently has in his/her machine.

As far as CPU power, AMD inappropriately chose "bulldozer" as their codename...I believe it's clear who has the bulldozer. lol

BL
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Old May 6, 2011, 06:39 PM   #124
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something AMD should be embarrassed of publishing
Why actually? If die size is around the same, overall chip performance is what really matters. Sure anyone could want to see AMD beating Intel clock-per-clock but if they can find different approach to fight against Intel and maybe even succeed in the long run - that's their choise.
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Old May 7, 2011, 06:49 PM   #125
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This new AMD CPU is complex that's for sure, how it will handle that's unknown, it's a bit harder for AMD if nobody supports AMD, it's still in Intel shadow one way or another.

AMD is going for the future here, home system don't need 8 cores or 6 because it's not so far supported like professional software is, sure some exceptions are there but still, that's workload for massive streams of data it's not about the same as high GHz does it, so this CPU will be just ok if proper prised but still if it's FX than i don't know for what it will be than.

Winrar supports max 4 cores "developer info", the rest is just HT bumping the data so AMD will go fast in Winrar that's for sure.
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