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#26 |
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I don't know that they'll ever "use it" so to speak, but that doesn't mean it won't be an issue. We may not be able to use lightning, but it can still be a serious pain in the ass.
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#27 | |
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But then again I am no engineer. I'm just an artist with a half degree in aerospace engineering.
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#28 |
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My second paragraph has nothing to do with the first one.FYI tunnelling depends on the material and the electric field across it (voltage/width of the material) and no logic can prevent that. But even if we prevent all the short-channel effects and static power consumption by using new materials, dynamic power consumption is going to be a big problem when integrating 10s of billions of switching elements in a chip.Adiabatic logic is just a solution to reduce dynamic power consumption and it is still in early stages of development.
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#29 | |
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![]() I think that combined with the layout of the chip itself should be enough to keep it from becoming an issue. |
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#30 | |
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Tunelling isn't the only problem. There are several other "short channel effects" |
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#31 |
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Lower voltage should reduce that issue also I would think. ALSO keep it more constant to keep it from drifting. Granted its still going to be a problem. I am looking forward to see what if any new material they use. We should know the direction they are heading in a year or so.
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#32 |
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I think the CMOS scaling will hit a wall at 6-4nm. If new materials/devices fails to improve the scaling beyond that, next step is to increase the performance / transistor by means of efficient architectures and IP cores. Re-configurable computing also looks promising.
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#33 | ||
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Note to self......use more fancy words. |
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#34 | ||
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I'm more shaky on these points but I think you also get strange inductance and capacitance effects, but don't ask me to nail those down. I think there are also issues of structural stability, migration of ions, etc, etc - at least using any kind of doped silicon. As hardcore pointed out, it's a long damn list. |
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#35 | |
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#36 | ||
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wiki Quote:
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#37 | |
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1. Fragments (which is what I believe) 2. Splits (which my professor believed) But at no time does it disappear and reappear like magic. ![]() On a side note I want to welcome Hardcore to the forums. Its nice to see someone new with brains.
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#38 | |
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According to the wave function of a particle, it simultaneously exists in many energy states at many different locations. In some cases, if you have the right conditions, you can increase the probability that the particle will manifest in a location consistent with it's wave function but which should be precluded by classical mechanics. That's the best I can do for you. This isn't an area encompassed by either of my graduate degrees so I'm kinda winging it. |
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#39 | |
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#40 | |
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Bastard. |
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#41 | |
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![]() Like I said I have some training in Aerospace engineering (few years of college). I wanted to be an avionics expert like my father at one time. Then I realized I hated math and loved drugs. Became an artist and forgot what planet I'm on half the time. |
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#42 | |
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If Intel's aiming for 2018 for 10nm i wonder what they are aiming for in 2020 and later? surly Intel, IBM, globalfoundries, TSMC etc are all looking in to what to use next?
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it all makes sense now
__________________
The pastafarian jesus |
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#43 | |
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or we just have no idea whats going on down at that level and what we assume is a solid electron is actually a collection of smaller particles that make a charge and when materials get small enough the particles can pass through other particle. Kind of how a bullet can't penetrate a kevlar vest but a arrow can. |
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#44 | |
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Last edited by TheMailMan78; Jul 27, 2011 at 05:05 PM. |
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#45 | |
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http://en.wikipedia.org/wiki/List_of...22_.2832_nm.29 most were released april 3rd, 2011 the same time the 10 core westmere's were released. remember this is a server roadmap and not a deskop roadmap. at any rate I seriously doubt the roadmap is for fiscal year, they are more than likely referencing the higher end sany bridge cpu's when they speak of late q4 2011. After all doesn't that mirror lga2011's release? |
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#46 | |
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bring on Ivy brige! I like to keep my eyes on the close future as a consumer, otherwise I'd never upgrade drooling voer what will be in 5+ years time...
22nm from 32nm should enable considerably higher clockspeeds IMO, would be nice to see some 6 core CPU's make it to 1155 too. also it would be a hec of a blessing if 1155 Ivy brige chips work on curent P/H67 and Z68 mobo's. Quote:
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#47 |
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When explaining the tunelling, it is better to treat the electron as a wave and use schrodinger's wave equation. Splitting it into smaller particles complicates the solution.
Uncertainty principle gives a simple explanation. For a narrow barrier and high electric field across it, probability of finding the electron on the other side of the barrier takes a finite non-zero value. |
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#48 | |
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Does considering splitting complicate things? Yeah but it COULD be an issue when getting down to 10nm as we were discussing (tunneling). The barrier will damn near be null at that point. As I said before it will be in the materials and design that will make or break a CPU when it gets that small. Intel has a tough road ahead IMO. |
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#49 |
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10nm is the channel length (physical), the thickness of the gate dielectric will be much less than that.Yes, Intel has a tough road ahead.
When the CMOS scaling hits a wall, all the major semiconductor companies should start making processors based on an open (license free) instruction set architecture which is more efficient than x86 and more scalable than ARM. ( my dream )
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#50 |
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just a matter of time
I'm of the belief that the time new tech hits the market those who put it out are r &d ing something 10 to 20 years beyound it. Consumer level is an inch above. End of life. We may not b able to see it like henery ford and his model t Couldn't see. The latest bmw 7 series but were on our way 2 nano tech just like the cartoons and movies. Our 2011 and bulldozers will b used in children toys and cofee makers(make u the perfect cup according to your dna)
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