3770K IHS removal and results

[graysky]

PART 1
Introduction
Feeling somewhat curious about the reports that inferior Thermal Interface Material (TIM) ships from the factory inside Ivy Bridge (IB) chips, I found myself taking my new 3770K out of the safety of its socket this afternoon and on to my desk where it went under the knife. About 15 min later, I finalized the divorce of its Internal Heat Spreader (IHS) and its Printed Circuit Board (PCB). It was surprisingly simple to do; a standard razor blade (0.009") and a little bit of patience was all that was required. After cleanup and application of fresh TIM, I sought to put a nice story together for you readers covering how to do procedure yourself and sharing my results and the methods used to arrive at them.

Removing the IHS from an i7-3770K
Maintain a level blade and gently insert it between the green part of the chip (PCB), and the silver part (IHS). I found it best to start on a corner. From what I've read, care needs to be taken not to scrap the PCB, as key parts of the chip reside very close to the surface. Slowly and gently, rock the blade between the two until it penetrates. Then slide it around the perimeter. See the pics to visualize the die so you don't push the blade in too far. The IHS will come off easily once you have completed severing the glue which is removed with gentle scraping with credit card or finger nails; isopropyl alcohol doesn't help much. When finished cleaning up both pieces, apply TIM to the die, place it back in the MB, and gently place the IHS on it. Lock it into place in the MB with the mounting bracket that will hold the IHS to the chip securely thus keeping you from having to glue down the IHS.





I'm a pretty big fan of Arctic Silver 5 (AS5) and used it both on the die, and on the outside of the IHS. My "factory" configuration had a good 120 h of load/idle cycles on it. As you probably know, AS5 has a breakin period associated with it...200 h according to Arctic Silver Incorporated. One can argue that this claim is valid based on the delta temp data.

Data Collection and Analysis
I wanted to generate robust and statically valid conclusions about the efficiency of entire process; results are drawn from a fairly large data set looking at the populations of temperatures and VID values. Temps and vcore values were collected via lm-sensors driven by a simple shell script which queried it every 2 sec logging the results to a file (see the end of this section for the script).

Example:

dts,vcc,temp,core0,core1,core2,core3,120mm_rpm,120mm_pwm,140mm_rpm,140mm_pwm
07-28-12 09:19:31 AM,1.280,66.0,58.0,63.0,65.0,60.0,1285,255,1225,255
07-28-12 09:19:34 AM,1.272,65.0,57.0,62.0,65.0,61.0,1300,255,1216,255
07-28-12 09:19:36 AM,1.272,64.0,59.0,63.0,66.0,59.0,1294,255,1226,255
...

These data were annotated and distributions were analyzed to see if the different TIMs under the IHS really makes a difference. Note that there are too many variable to control for this sort of analysis to be 100 % iron clad. For example, TIM spreading variations, mounting techniques, variations in hardware, etc. Even room temp can't be rigorously controlled. My office is air conditioned and ranged from 75-77 F when I ran the stress tests. In retrospect, I would have located the PC in my basement which has very consistent ambient temps but hind sight is always 20/20!

Methods of Stressing
I use linux, but key stress testers are cross platform. Intel BurnTest for windows is based on linpack from Intel which is available for many platforms. The settings I used were 25k problem sizes and 25k leading dimensions with 4 KB alignment.

On top of linpack, I ran a compile job looped in the background (nice=19) set to use 8 threads to further scarfs-up any unused CPU cycles.

System Specs and Settings
Asus P8Z77-V Pro
Intel 3770K @ 45x100
Cooling is an NH-D14 with both fans; my system manages their speed but they are both running on max for the stress tests (1,200 RPM for the 140mm and 1,300 RPM for the 120mm).

The BIOS is running using a vcore in offset mode so the vcore is automatically controlled by the BIOS and is dependent on load. Mine is stable with a setting of +0.0200 and here are the other key voltages and settings in case you're wondering:

VCCSA Voltage = 0.92500
CPU PLL Voltage = 1.5500
PCH Voltage = 1.06000
CPU Load-Line Calibration = Ultra High
CPU Current Capability = 140 %
CPU Power Response = Medium

Results
I ran the stress test described above for ~2 h period and used the geometric mean of the temps per core as the "average" temperature over that time period. I repeated this for a total of 4 nights, but lost the data on day 1 due to an overwrite on my part! Here are the average corresponding temps per day; there is a nice decrease out to day 3 where it more or less plateaus off. Perhaps that is the AS5 "breaking-in." Also note the error bars correspond to the measured ambient temp which ranged between 75-77 F or 1.1 C. You can see that some values at day 3 and 4 are not different when accounting for this:


As well, here is a plot of the delta temp, that is, the values subtracted from the stock results indicating the magnitude of temperature decrease:


And to be sure this horse has been beaten well after it died, here are the results compiled in a table:


Conclusion
For this example, a decrease in load temps was observed after delidding an Intel 3770K and replacing the factory TIM with AS5. The magnitude of the temperature reduction was not even across all cores, and ranged for -2C to -12C. The data are consistent with Arctic Silver Inc.'s claim that the TIM requires a break in period. This has to be one of the cheapest modifications to gain lower operating temperatures which can be converted into higher voltage and likely higher clock rates. The unevenness of the decrease is puzzling. Since the overall rank order of temps was retained after the TIM replacement, perhaps it has to do with some physical unevenness in the IHS, in the base of the HS, or on the CPU die itself. Investigating this is beyond the scope of this exercise.

Supporting Data
Link to my shell used to log the data.
Link to my shell script used to run gcc in the background.
Link to the entire data file (tab separated) should you wish to dig into it.

PART 2
Introduction
The above analysis was conducted using both a non-lapped IHS on the CPU and a non-lapped heatsink. I have since lapped both parts and repeated the experiment. My results seem to confirm that lapping these CPUs give minimal albeit real benefits. Others have reported no gains.

Lapping Parts
The process of lapping in detail will not be reviewed here, but in summary, one uses wet/dry sandpaper and a flat surface (glass usually) to slowly and iteratively grind an uneven surface. The goal of lapping is not be to make a mirror surface, rather, it is to make flat surface.

Lapping setup:


Heatsink lapping (220 grit --> 320 grit --> 400 grit --> 800 grit --> 1000 grit). Read this composite pic from left-to-right and from top-to-bottom:


As evident in the photos, the base of the NH-D14 is actually quite flat from the factory.

IHS lapping ( 400 grit --> 800 grit --> 1000 grit). Read this composite pic from left-to-right and from top-to-bottom:


As evident in the photos, the IHS on this 3770K was quite concave, that is, higher in the middle than elsewhere. "Flatness" was achieved in this case when no more silver color remained on the IHS.

Stress Testing
In addition to the linpack+gcc method described above, mprime (this is the linux version of prime95) running large FFTs was coupled with the same gcc compile stress to give another endpoint. By default, mprime runs with a background nice level (nice=19) and gcc ran with priority (nice=10). This is in contrast to the linpack+gcc setup where linpack ran with a higher priority and gcc ran with a background priority. This was by design.

In the linpack stress, gcc was employed to add further stress since linpack does not stress all cores evenly during a given run. In contrast, mprime does a very efficient job leveling load across all cores for a given calculation. Here gcc was given priority over mprime since the very nature of compiling code will lead to uneven usage.

Results
Rather than showing a per-core analysis which would make for a rather busy graph (4 cores x 2 conditions), a more simplistic "Lapped" and "Non-lapped" average results across all 4 cores is shown for each of the stress methods:


The delta temp spread for the averaged results ranged from 0 to -9 for the mprime+gcc experiments and from -1 to -12 for the linpack+gcc experiments.

Each line is relate to the factory TIM/unlapped result represented by the y=0 dashed black line. Again, these are delta temps which are relative to that factory result. The pink line shows the average drop in temp across all 4 cores for the unlapped results while the blue line shows the average drop in temps across all 4 cores for the lapped IHS and for the lapped HS. The data show a real but trivial difference after lapping both parts for most days. The exception being in the linpack+gcc stress on day 3. Here the average deltas are within error of each other based solely on the fluctuation in ambient temp.

Conclusion
Based on these data, lapping an i7-3370K and the heatsink used to cool it produces minimal benefits in heat dissipation gains.

[TRWOV]

great job. subed

[adulaamin]

Looking forward to your results!

[Damn_Smooth]

Great thread. Thanks for doing this.

[Sinzia]

Subb'd

[Millennium]

Just bumping for sub.

Please post results after 60 hours and 120 hours (and maybe something sooner) for comparison

Also what TIM did you use? cheers

[graysky]

Originally Posted by Millennium

Just bumping for sub.

Please post results after 60 hours and 120 hours (and maybe something sooner) for comparison

Also what TIM did you use? cheers

Yeah, I have collected data on 0 h and 12 h so far. No changes there.
I used Arctic Silver 5. Yeah, I know there are better ones out there but I had a tube of this on hand and used it. If the differences are to my liking, I can always pull the HS and IHS, clean them off and repeat with something else like Liquid Pro or Ultra or whatever.

[m1dg3t]

You beat me to it! lol Nice post

[Frogger]

SUBed will be waiting for your results.... thinking about an IB upgrade myself ! This might just be the thing to to with a new chip..

[scaminatrix]

Very impressive. Subbed.

I got some Shin-Etsu thermal tape here from marvelous211's old supply, let me know if you want a bit to try with

[DOM]

ive done this but wont do it again cuz it doent work to good with ln2 turned a 6.7ghz to like a 6

but it does help with themps for a reg cooling

[boogerlad]

You're going to have very bad contact with no ihs because it appears you didn't remove the cpu retention clamp. Also, it appears you have way too much tim for no ihs.

[graysky]

Originally Posted by boogerlad

You're going to have very bad contact with no ihs because it appears you didn't remove the cpu retention clamp. Also, it appears you have way too much tim for no ihs.

Are you addressing me? I do have the IHS, see pics. Also, why in the world would I remove the retention clamp? It is the only force holding the IHS to the die!

[boogerlad]

Oh sorry, I misread this as running ihs-less. You just replaced the tim. Nevermind then.

[james888]

Another sub.

I read a review some where, where they used Coollaboratory Liquid Pro thermal paste to connect the ivy chip to the ihs. This stuff makes a literal metal bond between the two objects. If I remember correctly, the chip then performed thermally like sandy.

[theoneandonlymrk]

Originally Posted by boogerlad

Oh sorry, I misread this as running ihs-less. You just replaced the tim. Nevermind then.

i got gidy untill i got to your post then realised my skip reading robbed me of ten mins damn,
no results yet either tut

[qubit]

Great thread. I await your results with interest.

[Sasqui]

^What qubit said!

So the IHS really is a heatsink leveling device. I'll be really surprised if you don't see some significant temp drops.

[graysky]

I am already... testing once per night (midnight to 4 AM) and on day 3 I see some good drops that vary from core to core. There is an effect of seeing thus far, better performance in general on day 2 vs. day 0 and better yet on day 3. Day 4 is tonight. I plan to have the data together and ready to "publish" Sunday.

[graysky]

OK! First thread updated with data and with conclusions. Enjoy!

[Frogger]

Originally Posted by graysky

Since the overall rank order of temps was retained after the TIM replacement, perhaps it has to do with some physical unevenness in the IHS, in the base of the HS, or on the CPU die itself. Investigating this is beyond the scope of this exercise.

Great results

^^^ probably... "perhaps it has to do with some physical unevenness in the IHS".. you could try lapping the IHS @ rerun to see result .....but might not be worth the time

[m1dg3t]

Thanks for updating! Can you compile more info over the next couple Weeks? I have heard some stories of temps increasing over stock after some useage.

[graysky]

Originally Posted by m1dg3t

Thanks for updating! Can you compile more info over the next couple Weeks? I have heard some stories of temps increasing over stock after some useage.

Since I saw that big disconnect in cores 0/1 and 2/3, I actually pulled the HS, cleaned, and reapplied, so the clock has started over

[Sinzia]

nice job, I cant wait to see what the next round of results will be!

[m1dg3t]

Originally Posted by graysky

Since I saw that big disconnect in cores 0/1 and 2/3, I actually pulled the HS, cleaned, and reapplied, so the clock has started over

Thnx! I'd be doing my own testing but I'm still witout a MoBo.... Damn iTX, no1 cares about us

I read some posts saying that temps were fine for a few days then shot up, prolly a case of PEBKAC? As I've also heard people say things were fine

I've had ~10c spreads on every multi core CPU I have seen, must be diodes. I take note of the hottest/coolest and then avg them out lol

I was thinking to run some ThermalRight cf3 instead of as5, I have both...