Intel, Samsung, TSMC Reach Agreement for 450mm Wafer Manufacturing Transition

[malware]

Intel Corporation, Samsung Electronics and TSMC have reached agreement on the need for industry-wide collaboration to target a transition to larger, 450mm-sized wafers starting in 2012. The transition to larger wafers will enable continued growth of the semiconductor industry and helps maintain a reasonable cost structure for future integrated circuit manufacturing and applications.


The companies will cooperate with the semiconductor industry to help ensure that all of the required components, infrastructure and capability are developed and tested for a pilot line by this target date.

Historically, manufacturing with larger wafers helps increase the ability to produce semiconductors at a lower cost. The total silicon surface area of a 450mm wafer and the number of printed die (individual computer chips, for example) is more than twice that of a 300mm wafer. The bigger wafers help lower the production cost per chip. Additionally, through more efficient use of energy, water and other resources, bigger wafers can help diminish overall use of resources per chip. For example, the conversion from 200mm wafers to 300mm wafers helped reduce aggregate emissions per chip of air pollution, global warming gasses and water, and further reduction is expected with a transition to 450mm wafers.

"There is a long history of innovation and problem solving in our industry that has delivered wafer transitions resulting in lower costs per area of silicon processed and overall industry growth." said Bob Bruck, vice president and general manager, Technology Manufacturing Engineering in Intel's Technology and Manufacturing Group. "We, along with Samsung and TSMC, agree that the transition to 450mm wafers will follow the same pattern of delivering increased value to our customers."

Intel, Samsung and TSMC indicate that the semiconductor industry can improve its return on investment and substantially reduce 450mm research and development costs by applying aligned standards, rationalizing changes from 300mm infrastructure and automation, and working toward a common timeline. The companies also agree that a cooperative approach will help minimize risk and transition costs.

"The transition to 450mm wafers will benefit the entire ecosystem of the IC industry, and Intel, Samsung, TSMC will work together with suppliers and other semiconductor manufacturers to actively develop 450mm capability," said Cheong-Woo Byun, senior vice president, Memory Manufacturing Operation Center, Samsung Electronics.

In the past, migration to the next larger wafer size traditionally began every 10 years after the last transition. For example, the industry began the transition to 300mm wafers in 2001, a decade after the initial 200mm manufacturing facilities (also known as "fabs") were introduced in 1991.

Keeping in line with the historical pace of growth, Intel, Samsung and TSMC agree that 2012 is an appropriate target to begin the 450mm transition. Given the complexity of integrating all of the components for a transition of this size, the companies recognize that consistent evaluation of the target timeline will be critical to ensure industry-wide readiness.

"Increasing cost due to the complexity of advanced technology is a concern for the future," said Mark Liu, TSMC's senior vice president of Advanced Technology Business. "Intel, Samsung, and TSMC believe the transition to 450mm wafers is a potential solution to maintain a reasonable cost structure for the industry."

The three companies will continue to work with International Sematech (ISMI), as it plays a critical role in coordinating industry efforts on 450mm wafer supply, standards setting and developing equipment test bed capabilities.

Source: Intel

[panchoman]

wait so intel cpus are going from 45nm to 450 mm in 2012?

[malware]

Originally Posted by panchoman

wait so intel cpus are going from 45nm to 450 mm in 2012?

Hehe, that's what people mean by 450mm wafer, not CPU die.

[HTC]

Originally Posted by panchoman

wait so intel cpus are going from 45nm to 450 mm in 2012?

Isn't 450mm supposed to be the size of the wafer that has the CPUs in?

EDIT

malware beat me to the punch ...

[kwchang007]

Originally Posted by panchoman

wait so intel cpus are going from 45nm to 450 mm in 2012?

The wafers, like discs of silicon, they produce the chips on is getting bumped up from 300mm to 450 mm.

Edit: I got beat like twice XD

[panchoman]

Originally Posted by malware

Hehe, that's what people mean by 450mm wafer, not CPU die.

ohhhhhhhhhhhh okay for a second i was like wtf

so what exactly will this affect?

[HTC]

Originally Posted by malware

Hehe, that's what people mean by 450mm wafer, not CPU die.

Imagine: a CPU cooler of that size ...

[kwchang007]

Originally Posted by panchoman

ohhhhhhhhhhhh okay for a second i was like wtf

so what exactly will this affect?

They can produce more cpu's per wafer, and that saves money....somehow idk the specifics.

[Morgoth]

Originally Posted by HTC

Imagine: a CPU cooler of that size ...

1 big waterblock and u save tons of weight XD

[farlex85]

Bigger wafers and smaller dies mean more cores per wafer I would assume. The die size will be down to 22nm by 2012, so they must be moving towards lots of specialized cores or something.

[PrudentPrincess]

Originally Posted by Morgoth

1 big waterblock and u save tons of weight XD

New Ultra 850 CPU Cooler! Over 100 heatpipes!

[hat]

Moore's law is running out...

[kwchang007]

Originally Posted by hat

Moore's law is running out...

Shhhh don't tell Intel that. It'll keep going, until they can't shrink dies anymore, then they'll have a problem.

[farlex85]

Yeah, its got a couple of years left though I presume. It might not get smaller than 22nm (the proposed shrink for the sandy bridge (successor to nahalem)). I dunno, I'm getting this off wiki, we'll just have to see I guess.

[kwchang007]

Originally Posted by farlex85

Yeah, its got a couple of years left though I presume. It might not get smaller than 22nm (the proposed shrink for the sandy bridge (successor to nahalem)). I dunno, I'm getting this off wiki, we'll just have to see I guess.

Well they have to go somewhere eventually. I think once we hit that wall companies are going to shift their attention from performance per watt to performance per transistor. Cause honestly they're going to only be able to stuff so much stuff in so much real estate. Or maybe they'll branch off into quantum computers which are supposed to have so much more capabilities if we could unlock them.

[broke]

I'm suprised that IBM is not in on this whole shebang

[Silverel]

Isn't IBM already at 32nm?

There's other material they can use to shrink past 22nm anyways. Not to mention Quantum computing will be coming into style in another 10 years or so. That should kick it up a few notches for Moore and his silly law.

[Mattgal]

does that means more heat?

[antzen]

omg...
i have seen a 450mm-ceramic-wafer on Semicon in Munich 8 years ago. this thing is huge.

i think, it's very difficult to handle such big wafers.
- they must be thicker than 300mm, so that they do not break so easily
- you need new carriers for production (act. 300mm: 25 wafers in 1 FOUP = heavy)
- you need new tools
....

[mdm-adph]

Originally Posted by kwchang007

Shhhh don't tell Intel that. It'll keep going, until they can't shrink dies anymore, then they'll have a problem.

Aye -- though all it means is that by that point the individual sockets on our MB's we'll be dealing with will start to get bigger and bigger and bigger... Or the chips themselves will get a lot thicker, either way.

[Morgoth]

Originally Posted by kwchang007

Shhhh don't tell Intel that. It'll keep going, until they can't shrink dies anymore, then they'll have a problem.

when the reached the minium size i geus the start increas the cpu size it zelf so more transistors fits on it

[kwchang007]

Well the problem with bigger chips means you need bigger sockets, more power, more heat is released, more cooling is need, the list goes on. The reason why we've seen such huge jumps in computing power relative to size and power consumption is because they can shrink dies. Then it'll cost more per chip and you need better interconnection stuff, yeahh bad stuff.

[yogurt_21]

wow! that's goign to be much more efficient. It'll reduce costs and emissions, not to mention reduce the man hours of manufacturing a set number of chips. talk about an ouch day for amd. lol