ATI's next gen GPU in next half of 2010

[Super XP]

Originally Posted by eidairaman1

sounds like speculation to me, also Nothing is true until the Military makes a statement about it.

Well that is the problem the Military will never let people know what's behind closed doors. For all I know they probably have a ATI Radeon HD 7890 running things

[Delta6326]

im waiting for my sweet 7850! hopefully some time in 2011 until then im sticking to my current rig

[a_ump]

Originally Posted by Super XP

Well that is the problem the Military will never let people know what's behind closed doors. For all I know they probably have a ATI Radeon HD 7890 running things

shit, you know they got GTX 780's n HD 8890's running in SLI-Fire lol

[eidairaman1]

Originally Posted by Super XP

Well that is the problem the Military will never let people know what's behind closed doors. For all I know they probably have a ATI Radeon HD 7890 running things

Nope, Not Needed. Probably have FireGLs, Quadros, Matrox, Itanium, Opteron, IBM, SUN running I suspect for systems.

[mastrdrver]

So I found this on the B3D forum last night......

http://forum.beyond3d.com/showpost.p...&postcount=571

Originally Posted by SKapusniak

It's because the properly ludicrous, entirely codename based, speculation, coming to a 'news' site near your as fact real soon now, surely surely has to be:

Southern Islands: R9xx on GloFo 32nm SOI process
Northern Islands: (aka Not Southern Islands) R9xx on TSMC 32nm (Oops!) Bulk process

[Super XP]

It's been confirmed, both TSMC and Global have scraped the 32nm process. Please note the date. This happend several days ago which gets be to believe 28nm Northern Islands GPU's are on schedule
This means AMD doesn't fully trust TSMC and are going to probably use Global Fo.. as a backup plan to make sure they get 28nm out the door. So once again, perhaps this Southern Islands thingy is HD 5800's re-fresh and we will see the real deal in Q1 2011.

Globalfoundries Scraps 32nm Bulk Fabrication Process.
Globalfoundries Will Not Make Chips Using 32nm Bulk Tech
[04/01/2010 02:46 PM]
..................“All of our efforts around next-gen graphics and wireless are focused on 28nm with HKMG and we no longer have a 32nm bulk process. We removed this off our roadmap due to lack of customer demand as most are making the jump from 40/45nm right to 28nm,” said Jon Carvill, the head of public relations at Globalfoundries.

Earlier Taiwan Semiconductor Manufacturing Company, the world’s largest contract manufacturer of semiconductor, decided to scrap plans for its 32nm bulk process technology, which caused several companies to reconsider their own roadmaps. TSMC’s 32nm bulk fabrication process did not feature HKMG and was largely considered as shrink of the company’s 40nm fabrication process..........................

http://www.xbitlabs.com/news/other/d...n_Process.html

This information also tells me that GloFo is going to do 28nm in the H2 2010.

GlobalFoundries to bring the "fastest" 28nm ARM Cortex-A9 design
http://www.brightsideofnews.com/news...a9-design.aspx

And here's more proof AMD is getting serious about 28nm and Northern Islands
AMD states the 28nm process is in good progress, second half of this year (2010) would be in Mass Production

AMD shows 28nm wafer GlobalFoundries to meet new card?
http://translate.google.com/translat...&sl=auto&tl=en

[entropy13]

Originally Posted by entropy13

Check my prior post in this thread, if we're assuming that what xbitlabs report is fact, then it will be a hybrid of sorts for AMD, 32nm initially spread out in both GF and TSMC, then 28nm afterwards, IN BOTH as well.

They're using the 32nm as a stepping stone of sorts and not exactly a "true progression" so to speak. I would think they're saying is that instead of sticking with TSMC with a problematic 32nm, why not spread it so to speak to GF too (with admittedly a problematic 32nm as well) so the yields would not be as bad.

This way they could:
-"Test the waters" with a 1) smaller process and 2) new architecture
-"Spreading it out" with both TSMC and GF to offset yield problems

Once they've accomplished that, we can expect next year a FULL lineup of 28nm cards. The 32nm serves as preparation for them. Think of it as the "4770 way", except bigger, and even the process (32nm) is only a "stepping stone" rather than the goal itself. Of course that's assuming that the problems get solved by that time.

I'll be quoting myself since the only thing I would be probably be wrong is with the 32nm process, with just some slight modifications.

With Southern Islands they could:
-"Test the waters" with a 1) smaller process and 2) new architecture
-"Spreading it out" with both TSMC and GF to offset yield problems

Once they've accomplished that, we can expect next year a FULL lineup of 28nm cards. Think of Southern Islands as the "4770 way", except bigger.

[nt300]

AMD did test water with HD 4770. Mybe they will do the same with HD 6770.

[entropy13]

Originally Posted by nt300

AMD did test water with HD 4770. Mybe they will do the same with HD 6770.

You're agreeing with me then.

[a_ump]

Originally Posted by nt300

AMD did test water with HD 4770. Mybe they will do the same with HD 6770.

don't you mean an HD 5XXX series card? as they released the HD 4770 during the HD 4XXX series, not an HD 5770 . hmmm so if they do try to test waters with a card i wonder which it'll be. HD 5650 isn't released i don't think, but that may be too small a chip?

[Dyno]

Originally Posted by _33

http://www.3dgameman.com/news/2010/0...-2nd-half-year
Apparently the new chips (code named Northern Islands) will feature a completely new architecture, as stated from the article linked above. So hopefully ATI will kick Nvidia butt in the tessellation field sooner than later, and 48 or 64 ROPs wouldn't hurt. Apparently from what is said is that the new HD6000 series will feature MIMD (Multiple Instruction, Multiple Data Parallelism) instead of SIMD (Single Instruction, Multiple Data Parallelism).

Apparently the MIMD part isn't big news, talking about MIMD shaders :P http://www.dvhardware.net/article38403.html

So you're telling me that the 5800 series lack tessellation due to hardware and not software "drivers"?

[cadaveca]

Originally Posted by Dyno

So you're telling me that the 5800 series lack tessellation due to hardware and not software "drivers"?

No, but this is why nVidia excels over ATI in tesselation. ATi has fixed hardware, nV's new gpu can use all shader units for tesselation, if needed. Winning in tesselation, in benchmarks, isn't exactly a real performance metric...to me it's the same as Phys-X affecting Vantage cpu scores, or the 2900XT have more mathematical power than the 8800GTX. Just because the potential is there, doesn't mean it will get used, as lowest-common denominator wins @ development houses most often.

[ToTTenTranz]

Originally Posted by cadaveca

No, but this is why nVidia excels over ATI in tesselation. ATi has fixed hardware, nV's new gpu can use all shader units for tesselation, if needed.

This seems to be a recurring mistake.

Fermi does not use the "CUDA cores" for tesselation and ATI does not use a fixed-function tesselator either.

What Fermi does have is one tesselator in each "Polymorph Engine", and there's one of those for each block of 32 shader cores. This means that the 480-shader Fermi has a total of 15 tesselators.

Cypress, Juniper and all the other DX11 gpus have only one tesselator. It's not fixed-function, though. The DX11 requires a programmable tesselator, which is why the RV600/RV700 tesselators aren't supported for DX11 tesselation.

[cadaveca]

Thank you so very much for taking the time to explain that to me. Of course, I'm just parrotting what others have said.

So, Fermi is basically 16 "main" cuda cores, each with many execution units, cache, RBE and tesellator? One "core" is disabled? And a single set-up engine to manage everything?

Haven't looked in the architecture specifics..I'm gonna get one any way.

[ToTTenTranz]

Originally Posted by cadaveca

Thank you so very much for taking the time to explain that to me. Of course, I'm just parrotting what others have said.

So, Fermi is basically 16 "main" cuda cores, each with many execution units, cache, RBE and tesellator? One "core" is disabled? And a single set-up engine to manage everything?

Haven't looked in the architecture specifics..I'm gonna get one any way.

(Note: all pictures come from the Digit-Life reviews.)


The Fermi has 4 "Graphics Processing Clusters"


And each GPC has 4 "Streaming Multiprocessors"


And each SM has 32 "Cuda Cores", which is what we call by "shader units".

This is a total of 16 "Streaming Multiprocessors" in Fermi with 32 cores each. For redundancy and/or lower power consumption, one SM is disabled in the GTX480 and two SM are disabled in the GTX470.

Each SM has its own tesselator unit (in the bottom, center), so the GTX470 has 14 tesselators and the GTX480 has 15.



ATI's Cypress has only one tesselator unit.

(on top, in the middle)




One interesting fact is that Fermi's tesselation performance is about 5x faster than Cypress'.
Given that the GTX480 has 15 times more tesselator units than the HD5870, we can conclude that ATI's tesselator has a performance about 2.5-3 times higher than the tesselators in Fermi..

This doesn't matter for the Cypress vs. Fermi war, of course, but it does provide us with a sneak-peek of how powerful ATI's next gen GPU could be at tesselation (should ATI decide to add more tesselators to the HD6000 family).

The tesselator in Cypress is, after all, the 5th generation of a unit that first was developed for the X360. No wonder it's a lot more effective than the tesselators in Fermi.

[cadaveca]

Huh. Very interesting, those diagrams. Seems that each maker has positioned thier tesselator in different locations within the rendering path, although ATI's diagram is quite abstract, whereas the Fermi diagram almost resembles a die shot.

That might translate in programmers having to chose progamming ideal for one, and not the other...ugh...maybe ATI's new gen can overcome that.

Those diagrams might kinda show why tesselation comes at such a performance drop, currently, too...seems part of nVidia's strength here is due to the tesselators location within the rendering path, and not just the number of units.


Thanks again for the wonderful explanation!

[ToTTenTranz]

Originally Posted by cadaveca

Huh. Very interesting, those diagrams. Seems that each maker has positioned thier tesselator in different locations within the rendering path, although ATI's diagram is quite abstract, whereas the Fermi diagram almost resembles a die shot.

That might translate in programmers having to chose progamming ideal for one, and not the other...ugh...maybe ATI's new gen can overcome that.

Those diagrams might kinda show why tesselation comes at such a performance drop, currently, too...seems part of nVidia's strength here is due to the tesselators location within the rendering path, and not just the number of units.


Thanks again for the wonderful explanation!

In my opinion, the decision to include such a huge tesselation power in Fermi was purely a "political" one.


nVidia knew that they could never make a GPU that was more computing-oriented and win to Cypress in the gaming-performance/transistor-count ratio at the same time.
There's lots of money involved in the computing thingie right now, so they went that way.

And, in order to create a "virtual win" for gaming, they picked one feature from DX11, pumped its performance to crazy high levels and now they're marketing that performance advantage as if tesselation was "all this is all about".


Some would call it playing dirty, and ATI could never pull this off... but nVidia can because it has a huge influence with developers through the TWIMTBP infection.
This means there's actually a chance that future DX11 games could have ridiculously high levels of tesselation in order to make nVidia's cards perform significantly better than ATI's counterparts -> even if ATI's cards have higher shading and texture mapping performance.



It would have been very difficult for ATI to predict this. They've been trying to bring tesselation to games for almost 5 years now and no one ever seemed to give a crap (having TWIMTBP infection in all AAA games made it too difficult nonetheless).
All of the sudden, their rival starts talking tesselation as if it was the next big thing and their hardware shows better performance in it..
Must have been frustrating for some people over at ATI.

[cadaveca]

No doubt. Vert statute comments there, opinion or not.

They really shouldn't have expected any less though...DX11 only brings so many features, so they'd have to pick one or two to excel at, and given current DX11 performance, most users aren't even gonna bother anyway, so in that regard, they(nV) are safe. By the time DX11 is really important, they'll have a whole new chip out.

And like I said before, IMHO, ATI took over AMD, not AMD bought ATi, and x86 licensing is why it went down the way it did... So while it may be a bit frustrating having to deal with the other side, they did something nV never will...make an x86 cpu. That's gotta hurt more for nV...Ati cna just release a new chip t ovoercome those problems...nV can't sell a cpu.

[Super XP]

Originally Posted by a_ump

don't you mean an HD 5XXX series card? as they released the HD 4770 during the HD 4XXX series, not an HD 5770 . hmmm so if they do try to test waters with a card i wonder which it'll be. HD 5650 isn't released i don't think, but that may be too small a chip?

No I think what he means AMD used 40nm for the HD 4770 to prepare and test it out for the later released HD 5870's and the HD 4870's used the older 55nm process.

Sure AMD could have released the HD 4870's using 40nm, but it probably would have turned out as Fermi turned out.

HD 4770 = 40nm process (AMD tests 40nm and learns its ins and outs)
HD 4870 = 55nm process (AMD used the older process because they knew its ins and outs)
HD 5870 = 40nm process (Thanks the HD 4770's testing, HD 5870 was a success )

[a_ump]

Originally Posted by Super XP

No I think what he means AMD used 40nm for the HD 4770 to prepare and test it out for the later released HD 5870's and the HD 4870's used the older 55nm process.

Sure AMD could have released the HD 4870's using 40nm, but it probably would have turned out as Fermi turned out.

HD 4770 = 40nm process (AMD tests 40nm and learns its ins and outs)
HD 4870 = 55nm process (AMD used the older process because they knew its ins and outs)
HD 5870 = 40nm process (Thanks the HD 4770's testing, HD 5870 was a success )

haha well from how he typed it up it sounded like he made it sound like ATI would release the HD 6770 to test 28nm, but that'd be releasing the next gen with a mid-range card. could be a pretty bad ass idea if it performs, have nvidia speculating what the top end is then blow away those expectations again.

[bobzilla2009]

Originally Posted by a_ump

haha well from how he typed it up it sounded like he made it sound like ATI would release the HD 6770 to test 28nm, but that'd be releasing the next gen with a mid-range card. could be a pretty bad ass idea if it performs, have nvidia speculating what the top end is then blow away those expectations again.

indeed, ATi have always had the plan of building up from the midrange to make the high end, and not the other way round. It would be interesting to see them do that next gen. Imagine ATi hitting the market with a very fast and very affordable card first, then bringing home some major pain later on. It would be pretty cool.

[RejZoR]

Originally Posted by Super XP

No I think what he means AMD used 40nm for the HD 4770 to prepare and test it out for the later released HD 5870's and the HD 4870's used the older 55nm process.

Sure AMD could have released the HD 4870's using 40nm, but it probably would have turned out as Fermi turned out.

HD 4770 = 40nm process (AMD tests 40nm and learns its ins and outs)
HD 4870 = 55nm process (AMD used the older process because they knew its ins and outs)
HD 5870 = 40nm process (Thanks the HD 4770's testing, HD 5870 was a success )

HD 4870 = 55nm process (55nm was used because at the time it was the common manufacturing process)
HD 4770 = 40nm process (AMD tests 40nm and learns its ins and outs)
HD 5870 = 40nm process (Thanks the HD 4770's testing, HD 5870 was a success )

It was actually this way... HD4870 came in first, then there was HD4770 and later on HD5870...

[nt300]

So maybe AMD may use 28nm with HD 5000 re-fresh for 1 or 2 cards like a HD 5790 or a HD 5690 say to test the porcess for better card later on.

[RejZoR]

It's always like this. They make a high end segment on a well tested manufacturing process and later on shrink the low or mid end card to a brand new, smaller manufacturing process. Mostly because smaller and less complex GPU's produce less defective chips and even if they do, the loss is very very low. Testing on huge and complex chips would yeld worse results and hiher costs for each defective chip.

[eidairaman1]

Also increase heat and power useage.