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9600XT @500/650 optimized memory timings

Discussion in 'Graphics Cards' started by Ripsaw, Dec 19, 2004.

  1. Ripsaw New Member

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    I have a Sapphire Radeon 9600XT 256mb card w/ Hynix 3.3ns ram. Using ATITOOL, I was able to optimize the memory timings at overclocked memory speed (624mhz). It would actually run @ memory of 330.75 with the below timings, but I backed it off one click (mhz settings increment/decrement in 6.75mhz steps) for added stability.

    Below is the card's BIOS dump log from RABiT v1.6 (a Radeon BIOS tuner) after I flashed-in the optimized settings, pertinent info in bold font:

    --------------------

    -- RaBiT v.1.6.1 build 346 --
    > RaBiT driver v.1.0.5 is loaded
    Read from file: 53248 bytes, ROM len: 53248 bytes
    -- Analyze ROM BIOS --
    > HEADER offs: 0x11E
    > PCIR struct offs: 0x18C
    > CRC table offs: 0x1B8
    > CLOCK table offs: 0x96E
    Core clock is 499.50 MHz
    Memory clock is 324.00 MHz

    Reference clock is 27.00 MHz
    > DRAM table offs: 0x1F8
    MEM info: MC_CNTL(0x00000071), memory size = 256 Mb
    > Memory config: 0x7180
    > TV table offs: 0xC569
    Active TV type: 'NTSC'
    > Hardware table: at 0x642, Rev.2
    hw_a: 0x350F, hw_b: 0x0000
    > DFP table offs: 0x654
    DFP table Ver.4, 2 preset(s)
    TMDS_PLL(1FBB0155), freq = 130.00 MHz
    TMDS_PLL(1FBB010F), freq = 200.00 MHz
    > Connectors Layout table offs: 0x64C
    Conn0 type = VGA, DDC = VGA, DAC = Unknown
    Conn1 type = DVI-I, DDC = DVI, DAC = Primary
    ASIC init: 0x75 = 0x08, 0x74 = 0x92
    -- ROM BIOS info --
    Desc: R9600XT P/N 113-AA12100-100-CE BIOS
    Info: V350AGP DGD1UN, ra010092.001 v611 , 2004/11/10 18:20
    Radeon family: Radeon 9600/9550/X600/X300 series
    -- Parsing hardware scripts: --
    > PLL script at 0x0534
    > PLL2 script at 0x05ED
    > INIT script at 0x02AC
    > MEMORY script at 0x0405
    -- Found hardware registers values: --
    > M_SPLL_REF_FB_DIV(0x03253004) at 0x0559
    > SCLK_CNTL(0x00007FF9) at 0x05B3
    > MC_TIMING_CNTL(0x1A14B322) at 0x043D
    > MC_CNTL(0x00000071) at 0x0407
    > MCLK_CNTL(0x001F1212) at 0x0588
    > MC_SDRAM_MODE_REG(0x31420042) at 0x0453
    > MC_READ_CNTL_AB(0x0BBD0BBD) at 0x032A
    > MC_REFRESH_CNTL(0x00009024) at 0x0324
    > MC_CHP_IO_OE_CNTL_AB(0x2FF52FF5) at 0x0437
    -- In BIOS memory timings --
    tWL = 1.0
    tCL = 4
    tCMD = 0 clock
    tSTB = equals tWrL + 1/2 clocks
    tRcdRD = 5
    tRcdWR = 3
    tRP = 6
    tRAS = 12
    tRRD = 2
    tR2W = CL + 2
    tWR = 2
    tW2R = 2
    tW2Rsb = Use tWR Rule
    tR2R = 2
    MemRR = 24
    tRFC = 22
    tRBS = CL + 3.5
    tERST = CL - 0.5
    tQSREQ = CL - 0.5
    tDQM = WL - 0.5
    tDQS = WL - 0.5
    tDQM_Adv = 1 clock earlier for WL 1 clock and more
    tDQS_Adv = 1 clock earlier for WL 1 clock and more

    -- Additional hardware info --
    SDRAM Mode Register: 0x42
    MCLK source select: MPLLCLK/2
    SCLK source select: SPLLCLK/1
    Chipset use A,B memory channels
    SDRAM specific: 2**13 rows, 512 columns
    SDRAM dynamic CKE is Enabled
    -- User changes followed --

    --------------------

    The specific optimizations made to factory BIOS memory timings, were as follows:


    - RAS to CAS Read Delay (tRcdRD) reduced from factory BIOS default of 6, to 5

    - Read to Write Turnaround time (tR2W) reduced from factory BIOS default of CL+3, to CL+2

    - Write to Precharge/Write Recovery time (tWR) reduced from factory BIOS default of 3, to 2


    NOTE: ATITOOL reports the tWL and tCL values shown in the above dump log, as 5 for tWL and 1.5 for tCL. This appears to just be an error in how ATITOOL and RABiT each report those values.
     
    Last edited: Dec 19, 2004

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