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Benefits of lowering the tRAS timing?

Discussion in 'Motherboards & Memory' started by Kantastic, Dec 31, 2012.

  1. Kantastic

    Kantastic

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    I've been trying to tighten the timings on my Samsung 30nm memory and noticed that I can set the tRAS timing as low as 12 without so much as an error in MemTest. I currently have it at 2133MHz 9-10-10-12-1T @ 1.5V. What I'm wondering is whether or not there are any benefits to having the tRAS timing so low. I've been reading conflicting answers, with some websites saying the tRAS timing should be close to the sum of the first 3 timings, and others saying that lower is better, period.

    Thoughts? :)
  2. qubit

    qubit Overclocked quantum bit

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    I'd say that lower is always better, if it works without errors.

    Think about it, all those timings actually refer to clock cycle delays, therefore the ultimate memory module and memory controller would give timings of 0-0-0-0-0T. This is clearly impossible in a real system of course, but is the theoretical limit that we're constantly striving for.
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  3. sneekypeet

    sneekypeet Unpaid Babysitter Staff Member

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    I used to run a set of Crucial's at 4-4-4-1 in the DDR2 days. There was a point to where the performance leveled off, I just kept lowering it because I could. ;)
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  4. Kantastic

    Kantastic

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    Great! I have it at 2133MHz 9-10-10-11-1T right now and it made it through 6 passes of MemTest without errors.

    THANKS GUYS! HAPPY NEW YEARS!
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