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Cyclos Semiconductor Announces First Commercial Implementation of Resonant Clock Mesh

Discussion in 'News' started by btarunr, Feb 21, 2012.

  1. btarunr

    btarunr Editor & Senior Moderator Staff Member

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    Cyclos Semiconductor, the inventor and only supplier of resonant clock mesh technology for commercial IC designs, today announced at the International Solid State Circuits Conference (ISSCC) in San Francisco, CA that AMD has successfully implemented Cyclos’ low-power semiconductor intellectual property (IP) in the AMD x86 core destined for inclusion in Opteron server processors and client Accelerated Processing Units (APUs). The adoption of the Cyclos resonant clock mesh IP to reduce power consumption demonstrates the commitment AMD has made to provide its customers with not only class-leading APU performance but also with the lowest possible power consumption.

    AMD’s 4+ GHz x86-64 core code-named “Piledriver” employs resonant clocking to reduce clock distribution power up to 24% while maintaining the low clock-skew target required by high-performance processors. Fabricated in a 32nm CMOS process, Piledriver represents the first volume production-enabled implementation of resonant clock mesh technology. “We were able to seamlessly integrate the Cyclos IP into our existing clock mesh design process so there was no risk to our development schedule,” said Samuel Naffziger, Corporate Fellow at AMD. “Silicon results met our power reduction expectations, we incurred no increase in silicon area, and we were able to use our standard manufacturing process, so the investment and risk in adopting resonant clock mesh technology was well worth it as all of our customers are clamoring for more energy efficient processor designs.”

    Cyclos resonant clock mesh technology employs on-chip inductors to create an electric pendulum, or “tank circuit”, formed by the large capacitance of the clock mesh in parallel with the Cyclos inductors. The Cyclos inductors and clock control circuits “recycle” the clock power instead of dissipating it on every clock cycle like in a clock tree implementation, which results in a reduction in total IC power consumption of up to 10%. Clock mesh power reduction is one area where EDA vendors have not yet delivered design solutions so the validation of resonant clock mesh technology via the AMD Piledriver design is welcome news to the IC design community. "High-performance processors have used clock mesh designs for years, but with growing emphasis on power reduction in both servers and mobile PCs, the traditional approach has become too power hungry," said Linley Gwennap, principal analyst of The Linley Group. "This announcement proves that the Cyclos resonant clock mesh technology provides meaningful power savings in real-world products. We expect other processor designers to adopt the Cyclos technology in applications where power reduction is important."

    Implementing inductors on-chip to resonate a clock mesh is a simple idea with complex implementation requirements. Cyclos has commercialized over 10 years of research to produce the first resonant clock mesh design solution that meets all the testability, reliability, dynamic frequency scaling, and quality assurance requirements of today’s ICs. “This is a major milestone for Cyclos Semiconductor,” said Marios Papaefthymiou, founder and President of Cyclos Semiconductor. “Now that the Cyclos technology is validated, we’re looking forward to expand into SoC designs via the design automation tools that are in development at Cyclos. We believe resonant clock mesh design will be a key enabler for GHz+ embedded processor IP blocks in next generation SoCs that also require ultra-low power consumption.”
  2. btarunr

    btarunr Editor & Senior Moderator Staff Member

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    Many Thanks to seronx for the tip.
  3. btarunr

    btarunr Editor & Senior Moderator Staff Member

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    Is Piledriver "Bulldozer done right"?
    • It's more energy efficient (look above)
    • It was always designed for very high clock speeds (its high-latency caches are designed to handle high frequencies when tied to both full-speed (CPU's clock speed), and NB-speed (uncore's clock))
    • IBM has an eye on the foundry process
    Where Intel spent billions perfecting its own technology, AMD is simply licensing them from numerous companies with similar technologies.
  4. Andy77 New Member

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    In that very same end, does it matter? Intel might have spent billions, but they got it ahead of AMD and consumers still prefer them over AMD. Look at finfet... GF and TSMC announced that finfets won't be "needed" until some lower process still years away when intel deploys it with Iyv, maybe it doesn't have a huge lead over Sandy but it has one that sways most of the hw communities to go with intel and blame AMD even further.

    Anyway, it's nothing new that AMD creates an environment with lots of partners around it. The same thing was done when they moved from FSB to HT.
  5. NC37

    NC37

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    So AMD should just close down and disappear? Yeah that leaves what...Intel alone with 100% of the market. AMD over the years has been a good tool to keep Intel innovating. Intel gets lazy, AMD catches up. Cycle repeats. I wouldn't be shocked to see it happen again on the CPU front. Just let AMD take it's time. The longer they do, the more Intel will let things slide.

    Now graphics front, that may heat up. Intel has long been lax about graphics. What is one of Intel's biggest markets...laptops! Here AMD comes in with designs that may not beat Intel in power but can beat them when it comes to "pretty." People like "pretty." Apple is the best example of that. Make it look good, and the person won't care if it can't do half of what another product can.

    So in otherwords, AMD doesn't need to make the fastest CPU in the world to compete directly with Intel. Just show they can make things look better for cheaper. Operating systems will just keep going more and more graphical, same with the net. Intel finally is feeling the pressure. But again, Ivy graphics won't be the solution, still too soon. Already confirmed it in benches. Year to two years, maybe Intel will have something if they really commit to it.
  6. GC_PaNzerFIN

    GC_PaNzerFIN

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    Of course it is more expensive when you are using much newer and better process. AMD, well GF actually, uses Gate First approach and are struggling with 32nm SOI when Intel is already mass producing 22nm CPUs on Gate Last process, with tri-gate transistors.

    They spend huge amount of cash in R&D, and they still make more profit in a year than AMD has done in last 10 years total. And quite frankly AMD themselves said they are stepping down from highend competition and focus on the APUs.

    After buggy phenom I and Bulldozer let downs I don't believe anything AMD PR people shovels out. Don't get me wrong, I want them to succeed so everyone can benefit from competition. Btw fun fact is Intel at least used to own sizeable chuck of AMD. Because it is cheaper for Intel to have sort of competitor than get accused of monopoly in the market.

    BTW, no word of improved single thread performance. I guess they forgot it, again.

    e:
    Intel: 54 billion dollars revenue in 2011
    AMD: 6.57 billion dollars revenue in 2011
    Last edited: Feb 21, 2012
  7. seronx

    seronx

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    AMD said nothing about focusing just on APUs. Notice this new article says 4+GHz Piledrivers. There is only a few Trinity APUs aiming beyond that. While the whole Vishera line up could be 4+GHz

    L3 is 2.4(95W)/2.6(125W)
    L2 is Half-clocked
    L1 is Full speed but has latency of 4 cycles <-- only one that is designed for very high clock rates

    NB speed is always near L3 speed since the NB controls L3

    Steamroller Technology Yet to be announced:

    Fully Depleted Planar Silicon on Insulator on 28nm Process
    Embedded Silicon Carbon for straining S/D(instead of Silicon Germanium)
    TSV
    T-RAM
    Faster Optical/Electrical interconnects
    and more etc.
    Last edited: Feb 21, 2012
  8. GC_PaNzerFIN

    GC_PaNzerFIN

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    Even my Pentium 4 was 4GHz, GHz race lost its meaning a long time ago.

    Maybe you should actually take a look at their plans, do you see highend CPUs? No. Do they talk about APUs everywhere? Yes.
    http://www.techpowerup.com/159870/A...Client-Roadmap-Big-Focus-is-on-APUs.html?cp=2

    http://www.anandtech.com/show/5492/amds-rory-read-outlines-amds-future-strategy

    e: another good one, from TPU as well http://www.techpowerup.com/155989/AMD-Still-Committed-To-x86-But-Not-In-High-End-Desktop.html
  9. seronx

    seronx

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    Bulldozer isn't a high clock design it is meant for extremely low clock rates that is why ARMv8 is designed after Bulldozer

    I see plenty of highend CPUs especially since Resonant Clock Mesh will be a lot useful for increasing clock rates

    AMD Opteron 6234 Interlagos 2.4GHz 16MB L3 Cache S...

    AMD doesn't talk about CPUs till near release to prevent Osbourn Effect. Steamroller CPUs aren't mentioned because of Piledriver CPUs.

    Do you know how much Steamroller CPU would gobble up sales from Vishera if AMD just straight up said hey enthusiasts you might not want to buy Vishera because
    Steamroller will have a 256b FlexFP instead of 128b FlexFP
    Steamroller will use TSV/T-RAM to achieve 64KB L1/2MB(smaller density) L2/12MB L3
    Steamroller will also have six modules

    Why would you annouce that? When you are going to release "Phenom II" might as well keep the "Phenom II X6" as a secret
  10. GC_PaNzerFIN

    GC_PaNzerFIN

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    ARM RISC processor designed after X86 architecture? That is the most ridiculous thing I have heard in years. :roll:
  11. seronx

    seronx

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    AMD's Bulldozer converts CISC to RISC remove that portion and make it fully RISC boom you got ARMv8

    Bulldozer can be applied to any Instruction Set x86/x64/ARM/EPIC(Itanium)/VLIW/etc.

    ARMv8 has 256 registers while Bulldozer has 64 Registers though there is some changes but that is beyond the point Bobcat/Bulldozer/ARMv8 are all based on the same thing Heterogeneous Systems Architecture

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