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Future Itanium and Xeon Processors Socket-Intercompatible

Discussion in 'News' started by btarunr, Nov 9, 2012.

  1. btarunr

    btarunr Editor & Senior Moderator Staff Member

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    In what could be the very first time two different machine architectures share a platform, future versions of Intel's Xeon and Itanium processors could be socket-compatible. Intel Itanium is based on the Itanium64 (IA64) machine architecture, while Xeon is x86-64 based. Intel plans to implement its common platform strategy with the next generation models of the two, that's "Kittson" Itanium, and "Haswell" Xeon.

    This level of convergence could make it easier for companies to deploy select amounts of Itanium and Xeon processors in their data-centers, to suit specific tasks, and save money on buying common platforms for both. Itanium processors are typically preferred for in mission-critical environments, where there's close to zero margin for error (think military, medical, and space-exploration); while Xeon is good at handling heavy serial processing loads (think servers, database management, cloud). Introduction of the converged platform is expected in the 2013-2015 time range, using Xeon "Haswell" launch as a point of reference.

    [​IMG] [​IMG]

    Source: X-bit Labs
     
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  2. btarunr

    btarunr Editor & Senior Moderator Staff Member

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    Many Thanks to NHKS for the tip.
     
  3. hellrazor

    hellrazor

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    Can't itanium just die already?
     
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  4. zAAm

    zAAm

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    I'll say it again and see if anyone complains this time 'round:

     
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  5. FordGT90Concept

    FordGT90Concept "I go fast!1!11!1!"

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    Good to see Intel is keeping IA-64 around. IA-64 is already appealing due to it's performance advantages. I also wouldn't be surprised at all if IA-128 is the first 128-bit processor on the market. Maybe it is coming sooner rather than later.
     
    Crunching for Team TPU
  6. Morgoth

    Morgoth

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    i want one :) but first i want to get a xeon phi co processor :D
     
    Last edited: Nov 9, 2012
  7. tacosRcool

    tacosRcool

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    will they do that with their other product lines? I don't think so
     
  8. Completely Bonkers New Member

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    I've never (personally) seen a real-world Itanium in application. Has anyone here? What was it used for? (Please, no "in theory" suggestions or links)
     
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  9. EpicShweetness

    EpicShweetness

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    That's what i wanna know can someone help Bonkers and I on this voyage to find a meaning to a 4 grand CPU such as this?
     
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  10. Morgoth

    Morgoth

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  11. Completely Bonkers New Member

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    YOU DESERVE AN INTERNET SLAP ;) FOR WASTING 4 MINUTES OF MY TIME with that useless video, robotic voice, and absolutely NO INFORMATION that is unique to Itanium.

    [​IMG]
     
  12. Delta6326

    Delta6326

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    I thought Itanium was for mission critical servers that they can't just simply turn off and switch to all new tech.
     
  13. eidairaman1

    eidairaman1

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    Ia 64 vs x8664
     
  14. MikeMurphy

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    Thanks for the thought-provoking post.
     
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  15. newtekie1

    newtekie1 Semi-Retired Folder

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    It is simple, it is an architecture that Intel doesn't have to share!
     
    Crunching for Team TPU 50 Million points folded for TPU
  16. Morgoth

    Morgoth

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    haha good:)
     
  17. xorbe

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    Did we forget about Alpha's EV6 bus and AMD's Athlon?
     
  18. cdawall where the hell are my stars

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    Nah he just wasn't around for it.
     
  19. Completely Bonkers New Member

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    Unfortunately, just like any processor, the Itanium cannot "beat" a mistake by the programmer or data entry person. No matter how many extra cores you throw at the problem... garbage in-garbage out.
     
  20. zAAm

    zAAm

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    Mmm. The availability features of the Itanium only applies to hardware, i.e. if a memory block becomes corrupt or a core fails or even when entire blades fail. Software logic errors cannot be fixed by a cpu, no matter what operating system you use.
     
  21. Completely Bonkers New Member

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    This thread is turning into the deaf leading the blind, or vice versa. I refer to my post #10 for anyone who has REAL experience of REAL WORLD application, not made up conceptual nonsense.
     
  22. zAAm

    zAAm

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    You're misunderstanding the meaning of the phrase "logic error". It's different from an insertion or deletion error that can be corrected with error detection and correction (ECC) methods.

    If I (as a computer engineer) mean to program a CPU to calculate 1 + 1 but I accidentally program it to calculate 1 + 2, that's a logic error. The CPU will NEVER be able to correct it (unless it's some kind of advanced AI that can predict what I MEANT to program :rolleyes: ) and will give an answer of 3 regardless.

    If however I program it correctly to calculate 1 + 1 and it gives an answer of say 405,353, an insertion or deletion error occurred somewhere in memory or cache. This kind of error can be detected and corrected by the CPU or O/S through checksums, parity bits and coding. That PDF you linked to just states that the Itanium has a number of ECC levels to ensure that even entire blocks of insertion/deletion errors can be corrected in memory, cache, bus etc. Regardless, it will still never be able to correct a logic error.

    What HP-UX does is software ECC on top of the already significant hardware ECC present in the Itanium. So it will use additional parity information to correct errors that were left uncorrected by the CPU.
     
  23. Morgoth

    Morgoth

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    does this ecc have anny use in pc's ? or only usefull in worstations/servers ?
     
  24. zAAm

    zAAm

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    It would have a use, but ECC takes up a lot of room in the CPU and memory controllers, which makes the CPU more expensive (you can fit less chips on a wafer). For desktop PC's, an application crash due to a hardware error would not be that bad in comparison (you might lose your current Word document progress for example), so it's usually not implemented to save costs.

    For mission critical use though, a crash might amount to millions of dollars in lost revenue. Also, hardware such as memory and cache has reached pretty decent reliability figures so the advanced ECC features found in Itanium at CPU and memory level is usually not needed for desktop applications.

    Error detection IS used in other desktop systems though, ex. Network Ethernet frames are sent with parity information to ensure the packet arrives without errors. I believe the PCI-Express standard also utilizes some primitive ECC features in normal operation - at least to detect errors if not correct them.
     
    Last edited: Nov 11, 2012
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  25. Steevo

    Steevo

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    Last edited: Nov 11, 2012
    10 Million points folded for TPU

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