1. Welcome to TechPowerUp Forums, Guest! Please check out our forum guidelines for info related to our community.

GLOBALFOUNDRIES Demonstrates 3D TSV Capabilities on 20nm Technology

Discussion in 'News' started by btarunr, Apr 2, 2013.

  1. btarunr

    btarunr Editor & Senior Moderator Staff Member

    Joined:
    Oct 9, 2007
    Messages:
    28,846 (11.09/day)
    Thanks Received:
    13,714
    Location:
    Hyderabad, India
    GLOBALFOUNDRIES today announced the accomplishment of a key milestone in its strategy to enable 3D stacking of chips for next-generation mobile and consumer applications. At its Fab 8 campus in Saratoga County, N.Y., the company has demonstrated its first functional 20nm silicon wafers with integrated Through-Silicon Vias (TSVs). Manufactured using GLOBALFOUNDRIES' leading-edge 20nm-LPM process technology, the TSV capabilities will allow customers to stack multiple chips on top of each other, providing another avenue for delivering the demanding performance, power, and bandwidth requirements of today's electronic devices.

    TSVs are vertical vias etched in a silicon wafer that are filled with a conducting material, enabling communication between vertically stacked integrated circuits. The adoption of three-dimensional (3D) chip stacking is increasingly being viewed as an alternative to traditional technology node scaling at the transistor level. However, TSVs present a number of new challenges to semiconductor manufacturers.

    GLOBALFOUNDRIES utilizes a "via-middle" approach to TSV integration, inserting the TSVs into the silicon after the wafers have completed the Front End of the Line (FEOL) flow and prior to starting the Back End of the Line (BEOL) process. This approach avoids the high temperatures of the FEOL manufacturing process, allowing the use of copper as the TSV fill material. To overcome the challenges associated with the migration of TSV technology from 28nm to 20nm, GLOBALFOUNDRIES engineers have developed a proprietary contact protection scheme. This scheme enabled the company to integrate the TSVs with minimal disruption to the 20nm-LPM platform technology, demonstrating SRAM functionality with critical device characteristics in line with those of standard 20nm-LPM silicon.

    "Our industry has been talking about the promise of 3D chip stacking for years, but this development is another sign that the promise will soon be a reality," said David McCann, vice president of packaging R&D at GLOBALFOUNDRIES. "Our next step is to leverage Fab 8's advanced TSV capabilities in conjunction with our OSAT partners to assemble and qualify 3D test vehicles for our open supply chain model, providing customers with the flexibility to choose their preferred back-end supply chain."

    As the fabless-foundry business model evolves to address the realities of today's dynamic market, foundries are taking on increasing responsibility for managing the supply chain to deliver end-to-end solutions that meet the requirements of the broad range of leading-edge designs. To help address these challenges, GLOBALFOUNDRIES is engaging early with partners to jointly develop solutions that will enable the next wave of innovation in the industry. This open and collaborative approach will give customers maximum choice and flexibility, while delivering cost savings, faster time-to-volume, and a reduction in the technical risk associated with developing new technologies.
     
  2. Jorge

    Joined:
    Jan 5, 2013
    Messages:
    763 (1.11/day)
    Thanks Received:
    81
    It's nice to see this tech being finally developed for mass production. This will bring more performance at reasonable prices. GloFo may finally be doing their part in the ecosystem to advance computing power.
     
  3. de.das.dude

    de.das.dude Pro Indian Modder

    Joined:
    Jun 13, 2010
    Messages:
    7,883 (4.86/day)
    Thanks Received:
    2,109
    FINALLY! 20nm in Glo-FO!
     
  4. itsakjt

    itsakjt

    Joined:
    Oct 9, 2010
    Messages:
    1,177 (0.78/day)
    Thanks Received:
    384
    Location:
    Kolkata, India
    AMD seems to benefit. :)
     
  5. theoneandonlymrk

    theoneandonlymrk

    Joined:
    Mar 10, 2010
    Messages:
    3,412 (1.99/day)
    Thanks Received:
    572
    Location:
    Manchester uk
    Looking good at glo fo ,I eagerly await some aggravated use of this tech.
     
    More than 25k PPD
  6. Vinska

    Vinska

    Joined:
    Jul 23, 2011
    Messages:
    1,419 (1.17/day)
    Thanks Received:
    1,259
    Location:
    Kaunas, Lithuania
    Globalfoundries? 20nm?
    AMD, die shrink Yer CPUs, please! :D

    AMD was pushing the 32nm process to the limit for quite some time now. They were doing miracles with it power-efficiency-wise, but now there is simply no room where to improve it on the 32nm. Going 20nm would really help them in that regard.
     
    Crunching for Team TPU
  7. jmgbjr New Member

    Joined:
    Apr 2, 2013
    Messages:
    2 (0.00/day)
    Thanks Received:
    0
    Not just 20nM but an actual competive advantage against Intel

    This is especially good news for AMD if they can apply this tech across their various tech product lines ( GPUs, APUs, CPUs, memory chips, etc). Certainly, Intel has the upper hand in offering smaller and smaller nodes faster than anyone else, but TSV gives AMD and other GF partners the ability to stretch out the comeptitive lifetime for using a particular node, especially as it becomes more and more difficult (and expensive) to produce ever smaller transistors. TSV sounds like it'll be really beneficial for AMD's future GPU since waiting for new nodes to become available and mature to acceptable production yields, is a major factor in why AMD and Nvidia have had to delay products over recent years. Now they can simply (or at least more simply than transitioning to a new node) add an additional layer to an existing GPU design to theoretially double performance. Of couse, I am no engineer and I may be over simplifying everything. There may be issues and limitations to TSV like higher heat production and voltage leakage or limits on how many layers are doable for a particular node type. Obviously, AMD won't be able to appy this technology to their products at least for a few more years, but hopefully it will come sooner rather than later, and give AMD the ability to update products more frequently and stay on schedule when releasing new parts.
     
  8. itsakjt

    itsakjt

    Joined:
    Oct 9, 2010
    Messages:
    1,177 (0.78/day)
    Thanks Received:
    384
    Location:
    Kolkata, India
    Yeah definitely. They were on a challenging competition with the 3rd gen Intel i7s being 22nm and they competing with their 32nm architecture. Now the competition should be justified after they release the 20nm CPUs.
     
  9. de.das.dude

    de.das.dude Pro Indian Modder

    Joined:
    Jun 13, 2010
    Messages:
    7,883 (4.86/day)
    Thanks Received:
    2,109
    infact amd said it will increase its core count in 8350 to 16!! there was a thread here somewhere....
     
  10. Frick

    Frick Fishfaced Nincompoop

    Joined:
    Feb 27, 2006
    Messages:
    10,881 (3.41/day)
    Thanks Received:
    2,387
    Just install the patch and you're set!
     
  11. itsakjt

    itsakjt

    Joined:
    Oct 9, 2010
    Messages:
    1,177 (0.78/day)
    Thanks Received:
    384
    Location:
    Kolkata, India
    8350 has 8 cores though. I hope they are gonna release an even mightier beast. Their Phenom and Athlon series were the best ever. FX is good but the others were more popular when they were released. After they decrease the TDP of their CPUs and improve the crossfire performance which many people are concerned about too, I bet their sales will rise up. :)

    Really? I mean the patch will make the 8 core to 16 core? :twitch:
     
  12. natr0n

    natr0n

    Joined:
    Jan 29, 2012
    Messages:
    2,006 (1.95/day)
    Thanks Received:
    1,038
    I've been working on 3 dimensional chip stacking for years.
    [​IMG]
     
  13. Frick

    Frick Fishfaced Nincompoop

    Joined:
    Feb 27, 2006
    Messages:
    10,881 (3.41/day)
    Thanks Received:
    2,387
    http://www.downloadmoreram.com/
     
  14. itsakjt

    itsakjt

    Joined:
    Oct 9, 2010
    Messages:
    1,177 (0.78/day)
    Thanks Received:
    384
    Location:
    Kolkata, India
    theoneandonlymrk says thanks.
  15. theoneandonlymrk

    theoneandonlymrk

    Joined:
    Mar 10, 2010
    Messages:
    3,412 (1.99/day)
    Thanks Received:
    572
    Location:
    Manchester uk
    Come on Microsoft , wave some stuff about ;).
     
    More than 25k PPD
  16. HumanSmoke

    HumanSmoke

    Joined:
    Sep 7, 2011
    Messages:
    1,507 (1.29/day)
    Thanks Received:
    528
    Typical GloFo, can't even get an April Fool's Day joke out on time :p
     
  17. Ikaruga

    Ikaruga

    Joined:
    Feb 18, 2011
    Messages:
    871 (0.63/day)
    Thanks Received:
    183
    Yes, they could finally catch up to the 32nm Sandy Bridge perhaps;)

    But putting jokes aside, this is great news indeed. We need much more competition on the CPU side, I hope AMD can make Intel sweat a little bit soon, and force them to make even better CPUs and drop prices:toast:
     
  18. The Von Matrices

    The Von Matrices

    Joined:
    Dec 16, 2010
    Messages:
    1,367 (0.95/day)
    Thanks Received:
    462
    I don't think this is as useful as it might seem. The main issue is that silicon is not a great heat conductor, so the lower layers of any multi-layer chip would be very constrained by TDP. This is probably the reason why they are introducing it to their low-power process. For a graphics card or a desktop processor producing even a moderate amount of heat, the lowest die would get too hot at what we consider to be standard clock speeds. The only die that can be allowed to produce any significant quantity of heat is the top one.

    I see multi-layer chips as being useful for eDRAM, which can be put on the lower layer(s) with the main processor on the top most layer. This is similar to Intel's Haswell and NVidia's Volta, except they use memory on the same package whereas this would be in the die stack and could potentially have a much much wider bus.
     
  19. hardcore_gamer

    hardcore_gamer

    Joined:
    Jan 25, 2011
    Messages:
    388 (0.28/day)
    Thanks Received:
    174
    Location:
    Fabry Perot cavity,AlGaAs-GaAs Heterojunction
    It is good to see that Industry is moving forward. Unfortunately, analog is not shrinking fast enough. I'm still designing circuits for 65nm process.
     
  20. sergionography

    Joined:
    Feb 13, 2012
    Messages:
    266 (0.26/day)
    Thanks Received:
    33
    with every new architecture from intel you will realize the drive behind ipc is almost getting to a dead end with how huge and complex the cores have become, what will you do next? add more decoders and widen the fpu? when already now they dont even see full utilization?
    the only thing intel have been doing is improve the cache subsystem with more entries and queues here and there, and improved prefetcher and branch predictors, but that will only go so far on this same old design, eventually they will need to make a radical redesign to the whole core to make room for improvement. bulldozer wasnt ideal, but surely it opened much more room for improvement, and i see the whole module idea going a long way even much longer after excavator

    this^
    nvidia already stated they will use stacked dram for their gpus in their future roadmap but its pretty much only to add capacity per chip(if i remember correctly i dont remember them saying it will be part of the same die did they?), which is expected in the next few years. but for gpus and cpus idk how likely this could work other than maybe having the l3 cache at the lower level and the cores on top, would make an interesting twist.
    on another I hope this makes ssds cheaper tho thats for sure!
     
  21. Ikaruga

    Ikaruga

    Joined:
    Feb 18, 2011
    Messages:
    871 (0.63/day)
    Thanks Received:
    183
    excuse me, but what?:) Are we talking about the same architecture?

    They completely redesigned the out-of-order execution (from scratch) in Sandy Bridge and the new one turned out to be pretty awesome tbh, it's one of the main reason it's ended up being one of the best CPUs ever of it's time (if not the one).
    They not only "improved" the cache but also added a new very high speed ring bus and other things like QuickSync or 6GBPs SATA to the chipset as well.
    Hell, it was beating the 980X Extreme in many of the tests, if this is the result when they don't introduce "radical changes", I have to admit I'm quite OK if they just go like that every time.
     

Currently Active Users Viewing This Thread: 1 (0 members and 1 guest)

Share This Page