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Intel, Micron Achieve Industry's Most Efficient NAND Product Using 3-Bit/Cell Tech

Discussion in 'News' started by btarunr, Aug 11, 2009.

  1. btarunr

    btarunr Editor & Senior Moderator Staff Member

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    Intel Corporation and Micron Technology Inc. today announced the development of a new 3-bit-per-cell (3bpc) multi-level cell (MLC) NAND technology, leveraging their award-winning 34-nanometer (nm) NAND process. The chips are typically used in consumer storage devices such as flash cards and USB drives, where high density and cost-efficiency are paramount.

    Designed and manufactured by IM Flash Technologies (IMFT), their NAND flash joint venture, the new 3bpc NAND technology produces the industry's smallest and most cost-effective 32-gigabit (Gb) chip that is currently available on the market. The 32Gb 3bpc NAND chip is 126 sq.mm. Micron is currently sampling and will be in mass production in the fourth quarter 2009. With the companies' continuing to focus on the next process shrink, 3bpc NAND technology is an important piece of their product strategy and is an effective approach in serving key market segments.

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    "We see 3bpc NAND technology as an important piece of our roadmap," said Brian Shirley, vice president of Micron's memory group. "We also continue to move forward on further shrinks in NAND that will provide our customers with a world-leading portfolio of products for many years to come. Today's announcement further highlights that Micron and Intel have made great strides in 34-nanometer NAND, and we look forward to introducing our 2xnm technology later this year."

    "The move to 3bpc is yet another proof point to the remarkable progress Intel and Micron have made in 34-nm NAND development," said Randy Wilhelm, Intel vice president and general manager, Intel NAND Solutions Group. "This milestone sets the stage for continued silicon leadership on 2xnm process that will help decrease costs and increase the capabilities of our NAND solutions for our customers."
     
  2. Mussels

    Mussels Moderprator Staff Member

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    so this is whats in the new intel SSD's eh?

    what the hell does 3 bits per cell mean anyway
     
  3. Easo

    Easo

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    Something normal human like you and me wouldnt understand.
     
  4. vanyots

    vanyots

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    3bpc means each cell holds 3 bits of information. It has 8 distinct levels that represent 8 possible variants of zeroes and ones in 3 bits.

    And this technology isn't for SSDs.
     
    Last edited: Aug 11, 2009
    25 Million points folded for TPU
  5. qwerty_lesh

    qwerty_lesh

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    They can make the smallest:cheapest 8GB chips in existance, hats off to IMFT.
    if this makes higher density flash based mp3 players and flash keys more common and cheaper im all for it. :toast:
     

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