1. Welcome to TechPowerUp Forums, Guest! Please check out our forum guidelines for info related to our community.

Intel Mulls Propagating PCI-Express 2.0 x2 Interface

Discussion in 'News' started by btarunr, Jul 20, 2011.

  1. btarunr

    btarunr Editor & Senior Moderator Staff Member

    Joined:
    Oct 9, 2007
    Messages:
    28,198 (11.43/day)
    Thanks Received:
    13,569
    Location:
    Hyderabad, India
    PCI-Express x1 met its match with the recent flood of devices such as 2-port SATA 6 Gbps and USB 3.0 controller chips that maintain their tiny package sizes thanks to a single-lane PCI-Express bus connection. The single-lane connection is already saturated with these kinds of devices: SATA 6 Gbps is moot with 250 MB/s per direction bandwidth of PCI-E 1.1, and could face bottlenecks with 500 MB/s of PCI-E 2.0, it is a similar case with USB 3.0 controllers. Use of PCI-Expresss x4, the bigger PCI-E bus standard, is a bad option as it increases PCI-E data pins by four times (significantly impacting chip package sizes), while eating into the limited lane budget of today's desktop chipsets.

    The next best thing is PCI-Express 2.0 x2. While 2-lane PCI-Express is hypothetically possible, it has never been implemented by motherboard manufactures, neither on client, nor enterprise platforms. PCI-Express' parent organisation PCI-SIG doesn't have a slot or port specification for PCI-E x2, either. Intel seems to be of the idea that PCI-Express 2.0 x2 will provide immediate relief to manufacturers of small-footprint devices such as inexpensive third-party USB 3.0 and SATA 6 Gbps controllers, it provides a total of 2 GB/s bandwidth, 1 GB/s per direction, which greatly alleviates bandwidth bottlenecks, while not significanly increasing chip pin-counts. PCI-Express 3.0 is still in its infancy, while implementing PCI-Express 2.0 x2 is the easier, short-term solution. It will cause minimal R&D overhead on manufacturers to implement it. PCI-E 2.0 x2 will fit nicely into the limited lane budget of today's desktop chipsets.

    Source: VR-Zone
  2. FordGT90Concept

    FordGT90Concept "I go fast!1!11!1!"

    Joined:
    Oct 13, 2008
    Messages:
    13,310 (6.35/day)
    Thanks Received:
    3,339
    Location:
    IA, USA
    Boo, use x4.
    1c3d0g, [H]@RD5TUFF and yogurt_21 say thanks.
    Crunching for Team TPU
  3. mastrdrver

    mastrdrver

    Joined:
    Feb 24, 2009
    Messages:
    3,098 (1.58/day)
    Thanks Received:
    560
    Intel fails at mulling. :laugh:
  4. The Von Matrices

    The Von Matrices

    Joined:
    Dec 16, 2010
    Messages:
    1,160 (0.89/day)
    Thanks Received:
    353
    I always wondered why x2 was missing since the link widths were 2^n. The addition seems logical to me.
  5. The Von Matrices

    The Von Matrices

    Joined:
    Dec 16, 2010
    Messages:
    1,160 (0.89/day)
    Thanks Received:
    353
    Since Intel's mainstream chipsets have only 8 non-graphics PCIe lanes and AMD's mainsteam chipsets have only 6 non-graphics PCIe lanes, having PCIe x4 for devices isn't feasible unless you're happy with only 1 add-in controller and nothing else on your board.
  6. Swamp Monster

    Swamp Monster

    Joined:
    Oct 22, 2010
    Messages:
    560 (0.41/day)
    Thanks Received:
    83
    Location:
    Latvia
    PCI-Express 2.0 x2 - another standard we don't need. Why not use PCI-E 3.0? "PCI-Express 3.0 is still in its infancy" is not argument good enough. If they have used it istead, then it would not be in it's infancy anymore.:shadedshu
  7. btarunr

    btarunr Editor & Senior Moderator Staff Member

    Joined:
    Oct 9, 2007
    Messages:
    28,198 (11.43/day)
    Thanks Received:
    13,569
    Location:
    Hyderabad, India
    Because companies as big as AMD, NVIDIA, and Intel can afford to test the waters with PCI-E 3.0, and bear the brunt in the event of a specifications flaw by shelling out millions of dollars in product recalls. Companies as small as JMicron, Renesas, VLI (VIA), etc., can't. Hence PCI-Express 3.0 is in its infancy. It took a long while after big companies implemented PCI-E 2.0 before small manufacturers followed. Hence, Intel wants to make things easy for itself as a desktop chipset manufacturer, and for those smaller companies.
    streetfighter 2 says thanks.
  8. D4S4

    D4S4

    Joined:
    Mar 27, 2008
    Messages:
    697 (0.30/day)
    Thanks Received:
    75
    Location:
    Zagreb, Croatia
    this is surprisingly nice (coming from a big evil corporation intel is)
  9. btarunr

    btarunr Editor & Senior Moderator Staff Member

    Joined:
    Oct 9, 2007
    Messages:
    28,198 (11.43/day)
    Thanks Received:
    13,569
    Location:
    Hyderabad, India
    One possibility is that Intel wants to spread cheap Thunderbolt controllers, and PCI-E 2.0 x1 is too little interface bandwidth, PCI-E 2.0 x4 is too many pins.
    Last edited: Jul 20, 2011
  10. R_1

    Joined:
    Dec 1, 2006
    Messages:
    449 (0.16/day)
    Thanks Received:
    39
    Use PCI-E 3.0 x1 instead!!!
    1c3d0g, Jizzler and devguy say thanks.
  11. arnoo1

    Joined:
    Oct 15, 2009
    Messages:
    742 (0.43/day)
    Thanks Received:
    124
    Location:
    Netherlands
    ow that's is why my corsair force3 120gb does a write speed of just 242mb/s instead the 500mb/s it's should do lol, i already know that because of maban|(thanks)

    now i have to wait for my gigabyte ga-z68x ud4 b3 and 2600k
  12. Jizzler

    Jizzler

    Joined:
    Aug 10, 2007
    Messages:
    3,392 (1.34/day)
    Thanks Received:
    632
    Location:
    Geneva, FL, USA
    I'd think a little more positively about this if I was hearing it from the companies or users who are supposedly affected. Otherwise, it reeks of evil ploy. Short term solutions have a tendency to be more trouble than they're worth.
  13. FordGT90Concept

    FordGT90Concept "I go fast!1!11!1!"

    Joined:
    Oct 13, 2008
    Messages:
    13,310 (6.35/day)
    Thanks Received:
    3,339
    Location:
    IA, USA
    Just because it takes an x4 slot doesn't mean it needs four electrical lanes to it. There's slots out now that have a x4 slot but only x1 electrical. Likewise, there's x16 slots with x8 electrical.


    If they want to add x2 to the PCI Express 3.0 standard, no one will really care. Adding it to PCI Express 2.0 though is a bad idea.
    Crunching for Team TPU
  14. btarunr

    btarunr Editor & Senior Moderator Staff Member

    Joined:
    Oct 9, 2007
    Messages:
    28,198 (11.43/day)
    Thanks Received:
    13,569
    Location:
    Hyderabad, India
    And you end up with x1 bandwidth.
  15. FordGT90Concept

    FordGT90Concept "I go fast!1!11!1!"

    Joined:
    Oct 13, 2008
    Messages:
    13,310 (6.35/day)
    Thanks Received:
    3,339
    Location:
    IA, USA
    Well, you're screwed either way. Either they need to put more lanes in the chipsets so they can power an x4 slot or they need to break the PCI Express 2.0 standard. Intel would rather break something that is perfectly fine and put a few more cents worth into their chipsets.

    Like I said, they should add x2 to PCI Express 3.0 and then push for using it. It makes no sense to revise a standard whom's days are already numbered.
    Crunching for Team TPU
  16. btarunr

    btarunr Editor & Senior Moderator Staff Member

    Joined:
    Oct 9, 2007
    Messages:
    28,198 (11.43/day)
    Thanks Received:
    13,569
    Location:
    Hyderabad, India
    No, you're not screwed either way. Currently, the 8 lanes of a Cougar Point can either be arranged as [4 * x1 + 1 * x4] or [8 * x1] port configurations. If you are dedicating that x4 to a single device that doesn't need 4 GB/s (2 GB/s /direction), you're wasing lanes. Grouping them as x2 is just organising it in a better way.

    Third-party GbE PHY chips don't use Cougar Point's GbE port (PCI-E 1.1 x1 @ 50 MHz), they take up one of those eight PCI-E x1 lanes, if you give away that PCI-E 2.0 x4 to a single device, you're left with just 3 lanes to offer as expansion slots or drive other onboard devices.

    "Putting more lanes on the chipset" means designing a new chipset right now. Not viable.

    Moving to PCI-E 3.0 would mean that Intel has to redesign a chipset, plus small manufacturers like JMicron have to spend tons of money designing for a new PCI-E specification, and carrying the risk of using a specification that hasn't been validated in the market by much bigger companies (like NVIDIA, AMD, etc.). This is something small companies won't do. So the easiest solution is PCI-E 2.0 x2. There's minimal R&D and risk by both parties.
    Chevalr1c says thanks.
  17. FordGT90Concept

    FordGT90Concept "I go fast!1!11!1!"

    Joined:
    Oct 13, 2008
    Messages:
    13,310 (6.35/day)
    Thanks Received:
    3,339
    Location:
    IA, USA
    What I meant was stop selling chipsets that don't have enough lanes to handle basic user requirements.


    I'd rather they release PCI Express 2.1 and 3.1 which have the x2 specification appended to it. That way you know what you have to look for if you intend to use an x2 device.
    Crunching for Team TPU
  18. Jizzler

    Jizzler

    Joined:
    Aug 10, 2007
    Messages:
    3,392 (1.34/day)
    Thanks Received:
    632
    Location:
    Geneva, FL, USA
    I think that's a bad idea too. Another size? Not unless manufacturers adopt open-ended slots on more of their motherboards. And I'm sure they'll love having more skus to fit the needs of their users. Two x2 on model A, an x4, and two x1 on model B, etc.

    Eventually all these smaller companies we've talked about will be on PCI 3.0, along with future chipsets with support. Shoe-horning in x2 now will undoubtedly extend the adoption of 3.0.

    Luckily I think the premise of this mulling is weak and nothing will come of it :)
  19. DanTheBanjoman SeƱor Moderator

    Joined:
    May 20, 2004
    Messages:
    10,553 (2.85/day)
    Thanks Received:
    1,383
    Since when is it 2^n? I don't see why x3, x5, x6 etc aren't possible. In fact I'm pretty sure all that's required is a BIOS update for the motherboard and possibly a firmware update on the card to support any amount of lanes.
  20. FordGT90Concept

    FordGT90Concept "I go fast!1!11!1!"

    Joined:
    Oct 13, 2008
    Messages:
    13,310 (6.35/day)
    Thanks Received:
    3,339
    Location:
    IA, USA
    Yup, and this is why PCI-SIG opted only for x1, x4, x8, and x16. If it ain't enough, you jump up. I wonder if Intel consulted with PCI-SIG at all. I bet PCI-SIG would have answered "no" right away.
    Crunching for Team TPU
  21. btarunr

    btarunr Editor & Senior Moderator Staff Member

    Joined:
    Oct 9, 2007
    Messages:
    28,198 (11.43/day)
    Thanks Received:
    13,569
    Location:
    Hyderabad, India
    Intel is a co-creator of PCI-Express. Intel, IBM, Dell, and HP are like veto powers in the PCI-SIG.
  22. newtekie1

    newtekie1 Semi-Retired Folder

    Joined:
    Nov 22, 2005
    Messages:
    19,653 (6.23/day)
    Thanks Received:
    5,830
    Just run an x4 link to a PCI-E switch and give yourself some more lanes. You aren't limitted just to the lanes provided by the chipset, bridge chips can and have been used to expand the lanes from the chipset to service more devices.

    I'm pretty sure PLX already has products for this purpose. I believe they make a switch that can take an x4 link from the chipset, and output 3 x4 links, or 1 x4 link and 8 x1 links, or just 12 x1 links.

    Yes, you can make the argument that all those links are still sharing the x4 uplink bandwidth and hence won't really gain a benefit from this. However, they work just like network switches. If only one device needs the x4 bandwidth, then it gets all that bandwidth. Yes, if more devices need that bandwidth they have to share it, but if you populate most of the links with low bandwidth devices such as onboard sound and USB2.0 controllers, and secondary LAN controllers, etc, then the high bandwidth device will get the bandwidth it needs.
    Jizzler says thanks.
    Crunching for Team TPU 50 Million points folded for TPU
  23. FordGT90Concept

    FordGT90Concept "I go fast!1!11!1!"

    Joined:
    Oct 13, 2008
    Messages:
    13,310 (6.35/day)
    Thanks Received:
    3,339
    Location:
    IA, USA
    I could see Dell and HP saying no. I doubt IBM cares.
    Crunching for Team TPU
  24. Hayder_Master

    Hayder_Master

    Joined:
    Apr 21, 2008
    Messages:
    5,173 (2.28/day)
    Thanks Received:
    638
    Location:
    IRAQ-Baghdad
    I see it's time to put SB agin, cuz many things now run over PCI-E so it should adding more PCI-E lines.
  25. mastrdrver

    mastrdrver

    Joined:
    Feb 24, 2009
    Messages:
    3,098 (1.58/day)
    Thanks Received:
    560
    Or you solve the problem with a board like the Asus P6T6 or P6T7. Sure you go through the NF200 chips, but you get a plethora of PCIe configuration options.

    This is why I love my P6T6. My next board will also be a 'Workstation' type board with a similar 6/7x PCIe slots. I don't care for anything else after having one. PCI is going away and I see no reason to buy any add in card that does not have a PCIe interface. So why bother with a board that offers something I have no use for?

    I know this isn't Intel, but they can bit me.

Currently Active Users Viewing This Thread: 1 (0 members and 1 guest)

Share This Page