The PCI-SIG finalized the specifications of PCI-Express 3.0 bus, the latest version of PCI. Like PCI-Express 1.x and PCI-Express 2.x, PCI-E 3.0 is designed to be backwards-compatible with devices that use older versions of the bus. Keeping up with the major version trend, PCI-E 3.0 doubles the theoretical bandwidth. PCI-Express 3.0 can push 1 GB/s per lane, per direction, double that of PCI-E 2.0. A PCI-Express 3.0 x16 slot would hence have its cumulative bandwidth at 32 GB/s. Apart from pure bandwidth increases, PCI-Express also uses the new 128b/130b data encoding scheme, which reduces protocol overhead significantly, allowing near-100% utilization of available bandwidth. To put this into perspective, PCI-Express 2.0 had a data-rate of 5 GT/s, but with its overhead, could only effectively transfer 4 GT/s. The new scheme allows utilization of all 8 GT/s of the bandwidth PCI-Express 3.0 has, resulting in a data-rate of 1 GB/s per lane, per direction. The PCI-E specification document is available to PCI-SIG members. It is expected that the first PCI-Express 3.0 compliant devices will come to be in 2011.