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Cadence Design Systems, Inc., a leader in global electronic design innovation, announced today that TSMC has selected Cadence solutions for its 20-nanometer design infrastructure. The solutions cover the Virtuoso custom/analog and Encounter RTL-to-signoff platforms.
The TSMC 20-nanometer reference flows incorporate new features and methodologies in both Encounter and Virtuoso that take into account newly important wire characteristics, timing closure and design size considerations.
For the custom/analog designer, Virtuoso technology supports new 20-nanometer constraints in the industry standard OpenAccess database, including G0 rules, interactive coloring for color-aware layout, a constraint-driven pre-coloring flow, odd-cycle loop prevention and detection, advanced Pcell abutment and support for local interconnect layers. Cadence Integrated Physical Verification System is an in-design technology that integrates the Cadence Physical Verification System within the Virtuoso platform.
For the digital designer, Encounter RTL-to-GDSII supports 20-nanometer rules, the new FlexColor double- patterning technology for correct-by-construction placement and routing, and Encounter RTL Compiler plus the GigaOpt optimization of Encounter Digital Implementation (EDI) System for better quality of results with a shorter turnaround time.
For signoff, the Cadence Encounter Timing System offers advanced waveform modeling and multi-valued SPEF for double-patterning RC extraction. Cadence QRC Extraction delivers a DPT-aware corners extraction technology that supports both LEF/DEF and GDSII flows. The Cadence Physical Verification System offers support of 20-nanometer double-patterning and incremental DRC correction, and TSMC rule decks are now available for the Physical Verification System. Encounter Power System provides accurate, basic and complex topology-dependent EM rules, and Litho Physical Analyzer and Litho Electrical Analyzer have been updated with 20-nanometer models for hotspot analysis and repair.
Finally, TSMC has adopted Cadence technology for its Custom Design Reference Flow, which demonstrates a methodology for designing custom and digitally assisted analog circuits through common technology setup and integrated concurrent analog and digital layout.
"Cadence is focused on providing our customers with the technologies they need to tackle the biggest challenges with today's complex designs, such as low power consumption," said Dr. Chi-Ping Hsu, senior vice president of the Silicon Realization Group at Cadence. "We have been working closely with TSMC and our mutual customers to develop comprehensive solutions to the challenges of 20-nanometer design. Our Virtuoso and Encounter 20-nanometer technologies are uniquely integrated to deliver a unified flow that addresses the most challenging low-power mixed-signal chips."
"Equipping design tools to fulfill 20-nanometer requirements is a complex endeavor that can be achieved only through close collaboration," said Suk Lee, senior director of Design Infrastructure Marketing, TSMC. "The 20-nanometer process required a new approach to make the ecosystem ready for the start of production designs as soon as the process node is ready. Our collaboration with Cadence covered complete mixed-signal and digital flows to ensure that the requirements for double patterning are implemented and validated. This will help our mutual customers achieve working chips as quickly as possible as they take advantage of this new process node."
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The TSMC 20-nanometer reference flows incorporate new features and methodologies in both Encounter and Virtuoso that take into account newly important wire characteristics, timing closure and design size considerations.
For the custom/analog designer, Virtuoso technology supports new 20-nanometer constraints in the industry standard OpenAccess database, including G0 rules, interactive coloring for color-aware layout, a constraint-driven pre-coloring flow, odd-cycle loop prevention and detection, advanced Pcell abutment and support for local interconnect layers. Cadence Integrated Physical Verification System is an in-design technology that integrates the Cadence Physical Verification System within the Virtuoso platform.
For the digital designer, Encounter RTL-to-GDSII supports 20-nanometer rules, the new FlexColor double- patterning technology for correct-by-construction placement and routing, and Encounter RTL Compiler plus the GigaOpt optimization of Encounter Digital Implementation (EDI) System for better quality of results with a shorter turnaround time.
For signoff, the Cadence Encounter Timing System offers advanced waveform modeling and multi-valued SPEF for double-patterning RC extraction. Cadence QRC Extraction delivers a DPT-aware corners extraction technology that supports both LEF/DEF and GDSII flows. The Cadence Physical Verification System offers support of 20-nanometer double-patterning and incremental DRC correction, and TSMC rule decks are now available for the Physical Verification System. Encounter Power System provides accurate, basic and complex topology-dependent EM rules, and Litho Physical Analyzer and Litho Electrical Analyzer have been updated with 20-nanometer models for hotspot analysis and repair.
Finally, TSMC has adopted Cadence technology for its Custom Design Reference Flow, which demonstrates a methodology for designing custom and digitally assisted analog circuits through common technology setup and integrated concurrent analog and digital layout.
"Cadence is focused on providing our customers with the technologies they need to tackle the biggest challenges with today's complex designs, such as low power consumption," said Dr. Chi-Ping Hsu, senior vice president of the Silicon Realization Group at Cadence. "We have been working closely with TSMC and our mutual customers to develop comprehensive solutions to the challenges of 20-nanometer design. Our Virtuoso and Encounter 20-nanometer technologies are uniquely integrated to deliver a unified flow that addresses the most challenging low-power mixed-signal chips."
"Equipping design tools to fulfill 20-nanometer requirements is a complex endeavor that can be achieved only through close collaboration," said Suk Lee, senior director of Design Infrastructure Marketing, TSMC. "The 20-nanometer process required a new approach to make the ecosystem ready for the start of production designs as soon as the process node is ready. Our collaboration with Cadence covered complete mixed-signal and digital flows to ensure that the requirements for double patterning are implemented and validated. This will help our mutual customers achieve working chips as quickly as possible as they take advantage of this new process node."
View at TechPowerUp Main Site