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We've been had.

Discussion in 'General Hardware' started by seronx, Apr 21, 2014.

  1. seronx

    seronx

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    AMD Kaveri's absolute best specifications are not;
    4 Cores with 1 x 256-bit Flex FPU and 1 x 128-bit MMX/Shuffle.
    8 CUs with 512 ALUs, 32 TMUs, 8 ROPs.
    128-bit DDR3.

    AMD's Kaveri's absolute best are;
    4 Cores with 2 x 256-bit Flex FPU and 1 x 256-bit MMX/Shuffle.
    16 CUs with 1024 ALUs, 64 TMUs, 16 ROPs.
    128-bit DDR3 + 128-bit DDR3/GDDR5 or 256-bit DDR3/GDDR5. (Wording for the combo is weird)

    ---
    https://i.imgur.com/fO8I6GO.png

    ^-- Steamroller from the imgur/discus leak. I have fixed it to a point where you can see that the actual and leak are the same.
    ----
    ----
    https://i.imgur.com/BLQ9Nuk.jpg
    https://i.imgur.com/sXNYo0K.jpg

    ^-- Tahiti's 16 CUs within Kaveri and measurement. Oddly, no one was surprised to find out Kaveri's CUs are 7.1 mm². For consideration;
    Tahiti: ~5.5 mm²
    Hawaii : ~4.9 mm²
    Pitcairn: ~4.4 mm²
    -----
    28nm-SHP is not less dense than TSMCs 28nm-HP(x) nodes. Instead it is very much more dense!

    28nm-SHP:
    ~100nm for CPP(source to drain length (divide by 4 to get Gate Length))
    ~80nm for 1x metal layers (double patterning)

    28nm SHP is the bulk version of IBM's 22nm SOI. AMD is also using HDL with this node so instead of the max 15 metal layers, AMD is only using 12 metal layers.

    Reasoning for AMD releasing a half disabled part;

    New Node, New Problems. Instead of affecting time to market for a fix, AMD disabled the problem parts then released it to achieve Time To Market requirements. We will eventually be getting Kaveri 2.0, sooner or later.
    Last edited: Apr 21, 2014
  2. eidairaman1

    eidairaman1

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    gives em time to release a full blown part, Intel has done such in the past aswell, so neither company is innocent of anything, they just want the money, just like how ATT, Comcast, Century Link, Dish Network, DirectTV, Windstream, Verizon, Sprint, Tmobile, AiO,Cricket are
  3. seronx

    seronx

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    It is at a huge scale though, pretty much half of all the 2.41 billion transistors are not active. Leaving only 1.2 to 1.4 billion transistors to be active, I only feel sorry for those who got Kaveri 1.0.
  4. theoneandonlymrk

    theoneandonlymrk

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    This is the way they All do it its how processes and architectures Are evolved. ........simples

    And not at all surprising to me.
  5. erocker

    erocker Super Moderator Staff Member

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    Why? Many people look at how something performs before they buy it as well as knowing that the product they buy will eventually be replaced with a better performing product.
    eidairaman1 says thanks.
  6. eidairaman1

    eidairaman1

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    Im taking it like most here would like a monopoly in processors where there is no innovation
  7. seronx

    seronx

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    Kaveri 1.0(KV-A1) and Kaveri 2.0(KV-B0) use the same 245 mm² die. No one with KV-A1's will be able to unlock KV-B0 functionality.

    If you bought KV-A1, you can either wait for Carrizo or get KV-B0.

    I don't think FM2+ supports the functionality of KV-B0 either, so possibly a new LGA socket would be required. Checking the BKDG, it doesn't seem FM2+ or FP3 supports KV-B0 functionality.

    The 60h-6Fh BKDG mentioned a SP2, which I think is the bigger BGA.

    KV-B0 -> SP1 / Carrizo -> SP2

    That would imply that Kaveri has an integrated Southbridge though. The plot thickens even more! So, obviously these disabled parts will continue to exist even throughout Carrizo.

    Kaveri 1.0 / Carrizo 1.0 -> FM2+ and FP3/FP4
    Kaveri 2.0 / Carrizo 2.0 -> LGA Socket and SP1/SP2
    Last edited: Apr 21, 2014
  8. HalfAHertz

    HalfAHertz

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    100% redundancy sounds too ridiculous to be true. Why would they even need to release cut down versions of the a10, if you have a backup of everything?
  9. seronx

    seronx

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    Time constraints with Time to Market?

    Steamroller "28nm" and Excavator "20nm"

    Steamroller =
    ~100 CPP / ~80 1x ML

    Excavator =
    ~80 CPP / ~64 1x ML

    To transition faster to market while having aggressive second halves. Simply release your APU half disabled then later in that year release the full SKU. Imo, This would only work if there was actually a problem for that node.

    Think of it like;
    Agena Dual-core (20xx)
    Agena Quad-core (20xx)
    Deneb Quad-core (20xx)

    I don't think Carrizo will have the same problems as Kaveri.
    Last edited: Apr 21, 2014
  10. FordGT90Concept

    FordGT90Concept "I go fast!1!11!1!"

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    I just want to know when AMD is going to push midrange DirectX 12 cards out.
    Crunching for Team TPU
  11. seronx

    seronx

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    A little offtopic but I think DirectX 12 encompasses: DX10, DX10.1, DX11, DX11.1, and DX11.2.

    Pretty much all newish GPUs support DX12. I think one of the bigger things that DX12 brings is that Pixel Shaders are becoming depreciated. While Compute Shaders are becoming a bigger thing. Expect newer GPUs to have no Geometry/Rasterizer/ROPs. Instead, bigger and faster L2s and non-fixed unit compute graphic pipelines.
    Last edited: Apr 21, 2014
  12. FordGT90Concept

    FordGT90Concept "I go fast!1!11!1!"

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    DX12 is basically Mantle in the API from what I read. I see DX12 NVIDIA GPUs on Newegg already but it doesn't list anything for AMD.
    Crunching for Team TPU
  13. seronx

    seronx

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    All those Nvidia GPUs are featureset 11_0, which means they support only DirectX 11*. While AMD GPUs support DX11.1 for SI and DX11.2 for CI/VI. DirectX 12 supports all DirectX 11 + superset GPUs.

    *Those products do not support DX11.1 or DX11.2, but can support DX12.
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  14. Vario

    Vario

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    Could it be possible the early kaveri aren't yielding well enough completely to run without die areas locked out?
  15. seronx

    seronx

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    It is probably something like that.

    KV-A0 dies were probably having a lot of device variation. Where most of the Kaveri dies were ending up not faster than Richland. So, AMD decides while they are working on that to tapeout KV-A1. With KV-A1 you have the same IPC and IPS as Richland for a more power efficient design. When KV-B0 comes out it might blow away KV-A1, which will disturb the market. Basically, AMD would need to release KV-B0 with a higher ASP than KV-A1 to recover from any losses. While keeping KV-A1 at the same ASP not to lose that markets profitability.
    Last edited: Apr 21, 2014
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  16. eidairaman1

    eidairaman1

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    by that time theyd slash the price of the older models

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