News Posts matching "Backwards Compatibility"

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Intel 9-series Chipset's Backwards Compatibility with Haswell Suspect

Intel's 9-series chipset, which is built for the company's next-generation Core "Broadwell" processor family, and slated for the second half of 2014, may face backwards-compatibility issues with current-generation Core "Haswell" processors, and the ability of current 8-series platforms to support "Broadwell," even though the two processor families share a common LGA1150 CPU socket, according to a VR-Zone report.

The report notes that a number of electrical connections between the CPU socket and chipset are different, and the chip follows a different power supply (as in power distribution within the chip/motherboard) than "Haswell." Such differences could pose backwards-compatibility issues. Although a generation ahead of Haswell, Broadwell isn't its immediate successor. Intel plans to roll out a refreshed Core "Haswell" processor family in a few quarters from now, which in addition to fully-integrated clocking mode, could introduce a few other platform changes. The report notes that 9-series chipset motherboards could be more compatible with Haswell (refresh), than the current Haswell platform. Intel 9-series chipset could introduce support for SATA-Express, the next big consumer internal storage interface that succeeds SATA 6 Gb/s.

Source: VR-Zone

PCI-Express 3.0 Hits Backwards Compatibility Roadblock, Delayed

PCI-SIG (Special Interest Group), the organisation responsible for development of PCI specifications announced that generation 3 PCI-Express (PCI-E 3.0), is off its target launch time from late-2009 to Q2 2010. Although work on the bus is almost finished, there seems to be problems with implementing backwards-compatibility with older generations of PCI-E. Assuming PCI-E 3.0 is standardised in Q2 2010, one can expect implementing products (motherboards and expansion cards supporting PCI-E 3.0) only by a year later.

PCI-E 3.0 packs features that overcome the bottlenecks of PCI-E 2.0, such as the removal of the 8P/10b encoding scheme that added at least 20% data overhead for the 5 GT/s PCI-E 2.0, reducing it to 4 GT/s effective. At 8 GT/s the new bus will have effectively twice the bandwidth.Source: TechConnect Magazine
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