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AMD's Fusion ''Ontario'' APU Chip Pictured

At the ongoing IFA event in Berlin, AMD displayed one of the first derivatives of its Bobcat low-power x86 processor architecture, codenamed "Ontario". This Fusion APU (accelerated processing unit), which is a combination of an x86 CPU and a DirectX 11 compliant GPU is built for low-power devices such as netbooks, handhelds, and tablets. AMD also showed off the chip package itself, which is roughly the size of a 1 Euro coin. The package, like AMD's mobile Athlon/Phenom processors, has no integrated heatspreader (IHS), but like the Intel Atom, uses a ball-grid array (BGA) to permanently fix itself to the system board.

AMD claims that the chip offers "mainstream performance" at less than half the die area (in this case, below 100 mm²), and a fraction of the power. Speaking of which, the "Ontario" Fusion APU has a TDP of 9W, while a higher-performance APU codenamed "Zacate", which is probably competitive with Intel's CULV processors, and is built for ultra-thin notebooks, nettops and slim all-in-one PCs, has a TDP of 18W. AMD claims that the two will ship (to OEMs, because these are not end-user products) in Q4 2010. For the desktop, AMD is developing the "Llano" Fusion APUs that are of a different form-factor and package altogether.


Bulldozer-based Orochi and Fusion Llano Die Shots Surface in GlobalFoundaries Event

The first official die-shots of the first Bulldozer architecture derivative, the eight-core "Orochi" Opteron die was displayed at Global Technology Conference, by GlobalFoundries, AMD's principal foundry-partner. While AMD did not give out a die-map to go with it, the structures we can make out are four Bulldozer modules holding two cores and a shared L2 cache each, a L3 cache spread across four blocks that's shared between all cores, the northbridge-portion cutting across the die at the center, and the integrated memory controller along its far-right side. Various I/O portions are located along the other three sides.

Next up is the Llano die. This is AMD's very first Fusion APU (accelerated processing unit) die. It is based on the K10 architecture and integrates a graphics processor and northbridge completely into one die. It precedes APUs based on the Bobcat architecture. Fortunately, there is a die-map at hand, which shows four K10 cores with dedicated 1 MB L2 caches per core, no L3 cache, an integrated SIMD array that holds 480 stream processors. The GPU component is DirectX 11 compliant. Other components include an integrated northbridge, integrated memory controller, integrated PCI-Express root complex, and HyperTransport interface to the chipset.
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