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AMD Orochi ''Bulldozer'' Die Holds 16 MB Cache

Documents related to the "Orochi" 8-core processor by AMD based on its next-generation Bulldozer architecture reveal its cache hierarchy that comes as a bit of a surprise. Earlier this month, at a GlobalFoundries hosted conference, AMD displayed the first die-shot of the Orochi die, which legibly showed key features including the four Bulldozer modules which hold two cores each, and large L2 caches. In coarse visual inspection, the L2 cache of each module seems to cover 35% of its area. L3 cache is located along the center of the die. The documents seen by X-bit Labs reveal that each Bulldozer module has its own 2 MB L2 cache shared between two cores, and an L3 cache shared between all four modules (8 cores) of 8 MB.

This takes the total cache count of Orochi all the way up to 16 MB. This hierarchy suggests that AMD wants to give individual cores access to a large amount of faster cache (that's a whopping 2048 KB compared to 512 KB per core on Phenom, and 256 KB per core on Core i7), which facilitates faster inter-core, intra-module communication. Inter-module communication is enhanced by the 8 MB L3 cache. Compared to the current "Istanbul" six-core K10-based die, that's a 77% increase in cache amount for a 33% core count increase, 300% increase in L2 cache per core. Orochi is built on a 32 nm GlobalFoundries process, it is sure to have a very high transistor count.Source: Xbit Labs

Picture of AMD ''Cayman'' Prototype Surfaces

Here is the first picture of a working prototype of the AMD Radeon HD 6000 series "Cayman" graphics card. This particular card is reportedly the "XT" variant, or what will go on to be the HD 6x70, which is the top single-GPU SKU based on AMD's next-generation "Cayman" performance GPU. The picture reveals a card that appears to be roughly the size of a Radeon HD 5870, with a slightly more complex-looking cooler. The PCB is red in color, and the display output is slightly different compared to the Radeon HD 5800 series: there are two DVI, one HDMI, and two mini-DisplayPort connectors. The specifications of the GPU remain largely unknown, except it's being reported that the GPU is built on the TSMC 40 nm process. The refreshed Radeon HD 6000 series GPU lineup, coupled with next-generation Bulldozer architecture CPUs and Fusion APUs are sure to make AMD's lineup for 2011 quite an interesting one.

Update (9/9): A new picture of the reverse side of the PCB reveals 8 memory chips (256-bit wide memory bus), 6+2 phase VRM, and 6-pin + 8-pin power inputs.Source: ChipHell

Bulldozer-based Orochi and Fusion Llano Die Shots Surface in GlobalFoundaries Event

The first official die-shots of the first Bulldozer architecture derivative, the eight-core "Orochi" Opteron die was displayed at Global Technology Conference, by GlobalFoundries, AMD's principal foundry-partner. While AMD did not give out a die-map to go with it, the structures we can make out are four Bulldozer modules holding two cores and a shared L2 cache each, a L3 cache spread across four blocks that's shared between all cores, the northbridge-portion cutting across the die at the center, and the integrated memory controller along its far-right side. Various I/O portions are located along the other three sides.

Next up is the Llano die. This is AMD's very first Fusion APU (accelerated processing unit) die. It is based on the K10 architecture and integrates a graphics processor and northbridge completely into one die. It precedes APUs based on the Bobcat architecture. Fortunately, there is a die-map at hand, which shows four K10 cores with dedicated 1 MB L2 caches per core, no L3 cache, an integrated SIMD array that holds 480 stream processors. The GPU component is DirectX 11 compliant. Other components include an integrated northbridge, integrated memory controller, integrated PCI-Express root complex, and HyperTransport interface to the chipset.

AMD Details Bulldozer Processor Architecture

AMD is finally going to embrace a truly next generation x86 processor architecture that is built from ground up. AMD's current architecture, the K10(.5) "Stars" is an evolution of the more market-successful K8 architecture, but it didn't face the kind of market success as it was overshadowed by competing Intel architectures. AMD codenamed its latest design "Bulldozer", and it features an x86 core design that is radically different from anything we've seen from either processor giants. With this design, AMD thinks it can outdo both HyperThreading and Multi-Core approaches to parallelism, in one shot, as well as "bulldoze" through serial workloads with a broad 8 integer pipeline per core, (compared to 3 on K10, and 4 on Westmere). Two almost-individual blocks of integer processing units share a common floating point unit with two 128-bit FMACs.

AMD is also working on a multi-threading technology of its own to rival Intel's HyperThreading, that exploits Bulldozer's branched integer processing backed by shared floating point design, which AMD believes to be so efficient, that each SMT worker thread can be deemed a core in its own merit, and further be backed by competing threads per "core". AMD is working on another micro-architecture codenamed "Bobcat", which is a downscale implementation of Bulldozer, with which it will take on low-power and high performance per Watt segments that extend from all-in-One PCs all the way down to hand-held devices and 8-inch tablets. We will explore the Bulldozer architecture in some detail.

AMD Announces Opteron 4000 Series Processors, Designed for Hyperscale Data Centers

At the GigaOm Structure Cloud Computing and Internet Infrastructure conference, AMD today announced availability of the new AMD Opteron 4000 Series platform. This is the first server platform designed from the beginning to meet the specific requirements of cloud, hyperscale data center, and SMB customers needing highly flexible, reliable, and power-efficient 1 and 2P systems. This platform is also available for high-end embedded systems such as telecom servers, storage, and digital signage, through AMD Embedded Solutions. Systems from Acer Group, Dell, HP, SGI, Supermicro, ZT Systems, and numerous other channel partners are expected beginning today and in the coming months.

AMD Sets the New Standard for Price, Performance, and Power for the Datacenter

AMD announces availability of a new server platform featuring the world’s first 8- and 12-core x86 processor for the high-volume 2P and value 4P server market. The AMD Opteron 6000 Series platform addresses the unmistakable needs of server customers today - workload-specific performance, power efficiency, and overall value - while delivering more cores and more memory for less money. Leading OEMs including HP, Dell, Acer Group, Cray, and SGI are introducing new systems based on this highly scalable and reliable platform.

“As AMD has done before, we are again redefining the server market based on current customer requirements,” said Patrick Patla, vice president and general manager, Server and Embedded Divisions, AMD. “The AMD Opteron 6000 Series platform signals a new era of server value, significantly disrupts today’s server economics and provides the performance-per-watt, value and consistency customers demand for their real-world data center workloads.”

AMD to Sample Bulldozer Architecture in 2010, Sets Product Priorities

As part of its Financial Analyst Day for 2009, AMD listed out its priorities for the year ahead, looking into 2010. While the company has lived up to its development targets for this year by releasing a full-fledged lineup of PC and server processors built on the 45 nm process, increasing its market share with graphics products, and releasing the first DirectX 11 compliant (back then referred to as 'next generation') GPU, the year ahead looks equally ambitious for AMD.

AMD set the following product priorities for 2010: to deliver four new winning PC platforms in the first half of 2010, improve battery life of its notebook platform, expand homegrown DirectCompute 11 and OpenCL developer tools, propagate DirectX 11 graphics to notebooks, launch the company's first 12-core Opteron processor, and more interestingly, sample the company's next-generation "Bulldozer" architecture to industry customers, along with sampling the company's first Fusion-design "Bobcat" processor, which integrates the CPU with GPU, along with sampling some of the company's first processors built on the 32 nm manufacturing process.

AMD Demos 48-core ''Magny-Cours'' System, Details Architecture

Earlier slated coarsely for 2010, AMD fine-tuned the expected release time-frame of its 12-core "Magny-Cours" Opteron processors to be within Q1 2010. The company seems to be ready with the processors, and has demonstrated a 4 socket, 48 core machine based on these processors. Magny Cours holds symbolism in being one of the last processor designs by AMD before it moves over to "Bulldozer", the next processor design by AMD built from ground-up. Its release will provide competition to Intel's multi-core processors available at that point.

AMD's Pat Conway at the IEEE Hot Chips 21 conference presented the Magny-Cours design that include several key design changes that boost parallelism and efficiency in a high-density computing environment. Key features include: Move to socket G34 (from socket-F), 12-cores, use of a multi-chip module (MCM) package to house two 6-core dies (nodes), quad-channel DDR3 memory interface, and HyperTransport 3 6.4 GT/s with redesigned multi-node topologies. Let's put some of these under the watch-glass.

AMD SSE5 Gets an Instruction-Set Expansion, Coins XOP (eXtended Operations)

AMD kept up with the SIMD processing standards Intel set by licensing its popular CPU instruction sets such as MMX, SSE, SSE2, and SSE3. The three were used as is by AMD, except for that AMD chose not to conform completely with Supplemental SSE3, SSE4 and its revisions (SSE4.1, SSE4.2). The company devised the SSE4A instruction set to feature with its K10 micro-architecture. SSE4A is a lighter version that features LZCNT (Leading Zero Count), POPCNT (bit population count), EXTRQ/INSERTQ and MOVNTSD/MOVNTSS (Scalar streaming store instructions). What's more, the company even decided back in 2007 that it would come up with SSE5, that then Intel sought to leave development with AMD.

In due course of time, Intel started development of AVX (Advanced Vector eXtensions) that enhances processing of FPU-intensive workloads. AMD gained interest in this technology, and is looking to make it compatible with the originally-conceived SSE5. The instructions that remain as part of the superset that doesn't include AVX is now referred to by AMD as XOP (eXtended OPerations). In addition to this, AMD will include FMA4 (Floating point vector Multiply-Accumulate). The new instruction sets make it to AMD's next-generation Bulldozer micro-architecture slated for 2011. Meanwhile, Intel's AVX makes it to the Sandy Bridge micro-architecture slated for 2010~11. AMD published the Programmer’s Manual document on 128-Bit and 256-Bit XOP, FMA4 and CVT16 Instructions, which can be read here (PDF).

AMD Demos 48-core Opteron Server

Having recently made its plans with the server market public, AMD demonstrated a 4-socket server featuring four 12-core, next-generation Opteron processors. That's 48 cores in all. The company has pulled its six-core Istanbul Opteron processors' launch from H2 2008 to Q2 2008, and is set to launch its Opteron 6000 series processors based on the "Magny Cours" architecture in 2010.

Processors in the series come with 8 or 12 cores. The company seems to be ready with a few of these, enough to put together a 4-socket demo system. While AMD did not run any benchmarks on the system, it managed to draw some attention due to the fact that there hasn't been so much parallelism in a 4-way server till date. On the course of its 2010 launch, the company may hold more demonstrations, perhaps with benchmarks to show how the platform compares to competing solutions from rival Intel. The "Magny Cours" processor will be the first in line for the company's G34 "Maranello" platform for AMD Opteron 6000 series processors with up to 16 cores, 4 sockets, and quad-channel memory interfaces per socket. The 16-core processor in the making is slated for 2011, is based on the Bulldozer architecture, and will be built on the 32 nm process.

Source: Heise c't Magazin

First Sketch of AMD Socket G34 Presented

AMD wants to leave the Barcelona (rather K10) debacle behind it as it moves closer to a newer processor architecture. This paves way for AMD to incorporate strong memory and system interface links. The G34 socket though touted to be a successor for the current socket 1207, is believed to be a standard socket for both enterprise and PC processors. AMD is working on a new CPU architecture codenamed 'Bulldozer'. Derivatives include monolithic 8-core and 12-core processors. The 12-core processor is now codenamed Magny-Cours, the 8-core part is called Sao Paulo. These processors could feature four parallel HyperTransport 3.0 interconnects, upto 12 MB of L3 cache and 512 KB L2 cache per core. It's known that AMD could be working on quad-channel DDR3 (both registered DDR3 under G3MX and unregistered). Socket G34 seems to have 1,974 pins.

The provision of four independent HyperTransport interconnects means that the fourth interconnect can be dedicated as a peer-to-peer interconnect between two sockets in a dual-socket setup, or its bandwidth split to form daisy-chains with multiple sockets. A prelude to AMD's Torrenza enterprise platform, which would allow use of several co-processors of different architectures including ClearSpeed to be embedded in workstations.

Source: DailyTech

AMD Unveils SSE5 for Bulldozer Core

AMD today announced further plans to innovate the x86 architecture by introducing SSE5, a new extension of the x86 instruction set that is designed to allow software developers to simplify code and achieve greater efficiency for the most performance-hungry applications. SSE5 will give developers additional capabilities to help maximize the performance of applications that have daily impact on consumers and enterprises, including high performance computing, multimedia and security applications.
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