News Posts matching "Bulldozer"

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AMD SSE5 Gets an Instruction-Set Expansion, Coins XOP (eXtended Operations)

AMD kept up with the SIMD processing standards Intel set by licensing its popular CPU instruction sets such as MMX, SSE, SSE2, and SSE3. The three were used as is by AMD, except for that AMD chose not to conform completely with Supplemental SSE3, SSE4 and its revisions (SSE4.1, SSE4.2). The company devised the SSE4A instruction set to feature with its K10 micro-architecture. SSE4A is a lighter version that features LZCNT (Leading Zero Count), POPCNT (bit population count), EXTRQ/INSERTQ and MOVNTSD/MOVNTSS (Scalar streaming store instructions). What's more, the company even decided back in 2007 that it would come up with SSE5, that then Intel sought to leave development with AMD.

In due course of time, Intel started development of AVX (Advanced Vector eXtensions) that enhances processing of FPU-intensive workloads. AMD gained interest in this technology, and is looking to make it compatible with the originally-conceived SSE5. The instructions that remain as part of the superset that doesn't include AVX is now referred to by AMD as XOP (eXtended OPerations). In addition to this, AMD will include FMA4 (Floating point vector Multiply-Accumulate). The new instruction sets make it to AMD's next-generation Bulldozer micro-architecture slated for 2011. Meanwhile, Intel's AVX makes it to the Sandy Bridge micro-architecture slated for 2010~11. AMD published the Programmer’s Manual document on 128-Bit and 256-Bit XOP, FMA4 and CVT16 Instructions, which can be read here (PDF).

AMD Demos 48-core Opteron Server

Having recently made its plans with the server market public, AMD demonstrated a 4-socket server featuring four 12-core, next-generation Opteron processors. That's 48 cores in all. The company has pulled its six-core Istanbul Opteron processors' launch from H2 2008 to Q2 2008, and is set to launch its Opteron 6000 series processors based on the "Magny Cours" architecture in 2010.

Processors in the series come with 8 or 12 cores. The company seems to be ready with a few of these, enough to put together a 4-socket demo system. While AMD did not run any benchmarks on the system, it managed to draw some attention due to the fact that there hasn't been so much parallelism in a 4-way server till date. On the course of its 2010 launch, the company may hold more demonstrations, perhaps with benchmarks to show how the platform compares to competing solutions from rival Intel. The "Magny Cours" processor will be the first in line for the company's G34 "Maranello" platform for AMD Opteron 6000 series processors with up to 16 cores, 4 sockets, and quad-channel memory interfaces per socket. The 16-core processor in the making is slated for 2011, is based on the Bulldozer architecture, and will be built on the 32 nm process.

Source: Heise c't Magazin

First Sketch of AMD Socket G34 Presented

AMD wants to leave the Barcelona (rather K10) debacle behind it as it moves closer to a newer processor architecture. This paves way for AMD to incorporate strong memory and system interface links. The G34 socket though touted to be a successor for the current socket 1207, is believed to be a standard socket for both enterprise and PC processors. AMD is working on a new CPU architecture codenamed 'Bulldozer'. Derivatives include monolithic 8-core and 12-core processors. The 12-core processor is now codenamed Magny-Cours, the 8-core part is called Sao Paulo. These processors could feature four parallel HyperTransport 3.0 interconnects, upto 12 MB of L3 cache and 512 KB L2 cache per core. It's known that AMD could be working on quad-channel DDR3 (both registered DDR3 under G3MX and unregistered). Socket G34 seems to have 1,974 pins.

The provision of four independent HyperTransport interconnects means that the fourth interconnect can be dedicated as a peer-to-peer interconnect between two sockets in a dual-socket setup, or its bandwidth split to form daisy-chains with multiple sockets. A prelude to AMD's Torrenza enterprise platform, which would allow use of several co-processors of different architectures including ClearSpeed to be embedded in workstations.

Source: DailyTech

AMD Unveils SSE5 for Bulldozer Core

AMD today announced further plans to innovate the x86 architecture by introducing SSE5, a new extension of the x86 instruction set that is designed to allow software developers to simplify code and achieve greater efficiency for the most performance-hungry applications. SSE5 will give developers additional capabilities to help maximize the performance of applications that have daily impact on consumers and enterprises, including high performance computing, multimedia and security applications.
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