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Cadence and Intel Collaborate to Enable a 14 nm Tri-gate Design Platform

Cadence Design Systems, Inc., a leader in global electronic design automation, and Intel Corporation, a world leader in computing innovation, today announced that the companies are collaborating to support Intel's 14 nm Tri-Gate process technology to enable customers of Intel Custom Foundry.

Cadence and Intel have together enabled the custom/analog flow, including Spectre APS, Virtuoso Schematic Editor, Virtuoso Layout Suite and Virtuoso Analog Design Environment for the 14nm Tri-Gate process. The companies are also collaborating on the development of the Cadence digital flow featuring Encounter Digital Implementation System, QRC Extraction Solution, and Tempus Timing Signoff Solution. Using these design flows, customers can leverage the power, performance and area benefits of Intel's 14 nm process technology.

TSMC and Cadence Strengthen Collaboration on 16 nm FinFET Process Development

Cadence Design Systems, Inc., today announced an ongoing multi-year agreement with TSMC to develop the design infrastructure for 16-nanometer FinFET technology, targeting advanced node designs for mobile, networking, servers and FPGA applications. The deep collaboration, beginning earlier in the design process than usual, will effectively address the design challenges specific to FinFETs -- from design analysis through signoff -- and will deliver the infrastructure necessary to enable ultra low-power, high-performance chips.

FinFETs help deliver the power, performance, and area (PPA) advantages that are needed to develop highly differentiated SoC designs at 16 nanometers and smaller process technologies. Unlike a planar FET, the FinFET employs a vertical fin-like structure protruding from the substrate with the gate wrapping around the sides and top of the fin, thereby producing transistors with low leakage currents and fast switching performance. This extended Cadence-TSMC collaboration will produce the design infrastructure that chip designers need for accurate electrical characteristics and parasitic models required for advanced FinFET designs for mobile and enterprise applications.

Cadence Announces Tapeout of 14 nm Test-Chip

Cadence Design Systems, Inc., a leader in global electronic design innovation, announced today the tapeout of a 14-nanometer test-chip featuring an ARM Cortex-M0 processor implemented using IBM's FinFET process technology. The successful tapeout is the result of close collaboration between the three technology leaders as they teamed to build an ecosystem to address the new challenges from design through manufacturing inherent in a 14-nanometer FinFET-based design flow.

The 14-nanometer ecosystem and chip are significant milestones of a multi-year agreement between ARM, Cadence and IBM to develop systems-on-chip (SoCs) at the advanced process nodes of 14 nanometers and beyond. SoCs designed at 14 nanometers with FinFET technology offer the promise of a significant reduction in power consumption.

TSMC Selects Cadence Virtuoso and Encounter Platforms for 20 nm Design Infrastructure

Cadence Design Systems, Inc., a leader in global electronic design innovation, announced today that TSMC has selected Cadence solutions for its 20-nanometer design infrastructure. The solutions cover the Virtuoso custom/analog and Encounter RTL-to-signoff platforms.

The TSMC 20-nanometer reference flows incorporate new features and methodologies in both Encounter and Virtuoso that take into account newly important wire characteristics, timing closure and design size considerations.
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