News Posts matching "Nehalem"

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IDF 2008 Day 1: Intel Nehalem Working at 3.2GHz Pictured

I promissed more details on Intel Nehalem yesterday, and now it is time to keep my word. During the first day of Spring IDF 2008, the guys over at HEXUS.net have pictured the first working sample of a quad-core Intel Nehalem processor operating at 3.2GHz (revision A1). The 1366-pin, 731M-transistor 45nm native quad-core model, utilizes 256KB of L2 cache for each core, as well as 8MB of L3 cache. The CPU also integrates triple-channel DDR3-1333MHz memory controller and SSE4 instructions. Like the new 533MHz Silverthorne-based Atom processors, Nehalem will also incorporate Simultaneous Multithreading (SMT) which is also known as Hyper-Threading (HT). Each physical core in a single Nehalem processor is paired up with its own virtual core. As a result, the quad-core processor will be detected to have eight cores (on the picture). Predictions say that this new architecture will offer around 30% better performance, on a clock-for-clock basis, when compared to Core 2, in a heavily-multithreaded environment - HPC and low-end servers, mainly. Current Intel roadmaps list the Nehalem launch date for Q4 2008, with a simulteanous rollout across servers and desktops.

Source: HEXUS.net, DailyTech

Intel 45nm Nehalem CPU Die Pictured

Intel Developer Forum (IDF) in Shanghai, China, officially opens its doors from April 2nd to April 3rd. Topics set to be covered at IDF Shanghai include Netbook, Nettop, Bloomfield (Nehalem), solid-state drives, QuickAssist (accelerators), system-on-chip (Tolapai), and USB 3.0. The pictures below are from one of these topics, the new quad-core Nehalem CPU, or more specificly its core. Intel's future Nehalem will bring a totally new system architecture and a next-gen platform architecture. It will come in new socket, and will be the first processor to have up to 8 cores and integrated DDR3 memory controller. Expect more details tomorrow.

Source: ComputerBase, CNET Blogs, VR-Zone

Intel Bloomfield Motherboard Up Close and Personal

Intel Smackover Motherboard Up Close and Personal

As Intel's next-gen 45nm Hi-k Nehalem CPU architecture codenamed Bloomfield is being planned for the fourth quarter of this year, it's time to see some pictures of the motherboard that will become home for these new processors. The board pictured below is an early reference sample codenamed "Smackover" (see picture 1). Smackover will be released in Q4 together with the Nehalem server parts and it will be a triple-channel DDR3 high-end workstation/gaming platform. The motherboard has single 1366-pin CPU socket, four DDR3-1333 slots, three of which being colored blue to signal the triple-channel support and two PCI-Express 2.0 x16 slots, likely bringing CrossFire to Intel's platform. The only heatsink installed is the one covering the ICH10 southbridge while the Tylersburg NB is left "naked". The board has no IDE or floppy connectors, but only six SATA 3.0 Gbps ports.

Source: TechConnect Magazine, Chiphell

Nehalem to Use Similar Cache Structure to Phenom

It looks like Intel has decided to adopt the same approach as AMD with the cache structure on its upcoming Nehalem processors, opting to go for small per-core L1 and L2 caches, with a large shared L3 cache. The new architecture will feature 64KB L1 cache per-core working in the same way as current Core 2 CPUs, but instead of a shared L2 cache each core will have 256KB of its own. All of the cores will then have access to a shared L3 cache of up to 8MB. AMD’s Phenom CPUs work in a very similar manner, such as the 9600, which has 256KB L2 cache per-core and a shared 2MB L3 cache. The exclusive L2 caches give each core a pool of fast-access memory, while the shared cache acts as a buffer to trap data and instructions other cores may have requested, allowing another core to access it more quickly than using the main memory.Source: Reg Hardware

Early Intel Nehalem Performance Projections Leaked

A leaked PDF from Sun Microsystems' website (which has now been removed) suggests that Intel could have something quite impressive up its sleeve with its upcoming Nehalem processor. The processor was already rumoured to feature three channels of DDR3 memory per core compared to two channels of DDR2 per core on AMD’s Barcelona and upcoming Shanghai CPUs, and it seems that could give the Nehalem quite a performance boost. Extrapolated figures from ZDNet based on data in the slide are shown in the graph below, and as you can see, the Nehalem on average scores twice as highly as a 2.3GHz Barcelona and almost 40% better than a 2.8GHz Shanghai in SPEC CPU tests. As always with benchmarks on unreleased hardware it’s important to remember that the data may not be accurate and synthetic benchmarks don’t always reflect real-world performance, but if these are at all reliable then Intel’s next generation of processors could be a huge leap forward.

Source: ZDNet

Intel Demonstrates First 32nm Chip and Next-Generation Nehalem Processors

Intel Corporation President and CEO Paul Otellini today outlined new products, chip designs and manufacturing technologies that will enable the company to continue its quickened pace of product and technology leadership.

Speaking to industry leaders, developers and industry watchers at the Intel Developer Forum (IDF), Otellini showed the industry's first working chips built using 32 nanometer (nm) technology, with transistors so small that more than 4 million of them could fit on the period at the end of this sentence. Intel's 32nm process technology is on track to begin production in 2009.

Intel Will Counter Barcelona with 1600MHz FSB Xeons

After hearing nothing about the 1600MHz FSB Xeons for several months VR-Zone tells us they will appear in Q4 this year. There will be 2 quad core Harpertown models at 2.8 and 3 GHz and a single dual core Wolfdale at 3.4 GHz. Additionally the cache is increased by 50% to 3MB per core. The faster FSB and increased cache will raise the bar even higher for Barcelona, however since both CPU's aren't available it is yet to be seen if this will be enough.

To support these new processors Intel will release the Seaburg chipset, it is not mentioned if the current chipsets will officially support the faster bus.
For a full list of new Wolfdales and Harpertowns visit VR-Zone.Source: VR-Zone

Intel pushes Nehalem Into H2 2008

Intel has revealed some information on their Nehalem processor in the latest roadmap updates. The 45nm Hi-K Nehalem-EP is based on 4-issue Intel Core micro-architecture technology, supports Simultaneous multi-threading and Multi-level shared cache architecture (L2 and L3). Nehalem-EP processor will arrive earlier than expected, in H2 2008, and will pair up with Tylerburg chipsets. EP stands for Efficient Performance, one of the new naming schemes for server platforms. It should mean good energy efficency on 1-2 processor sockets. There are also Mission Critical (MC) markings, for best RAS from 2-512 processor sockets, Expandable (EX) is for RAS from 2-32 processor sockets as well as Entry (EN) on 1-2 processor sockets to better align with future IT usage.Source: VR-Zone
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