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Synopsys and TSMC to Deliver 16-nm Custom Design Reference Flow

Synopsys, Inc., a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced that it has collaborated with TSMC to provide support for voltage-dependent design rules in TSMC's 16-nm Custom Design Reference Flow. As part of TSMC's custom design infrastructure, TSMC has also certified Synopsys' Laker custom design solution and circuit simulation tools that deliver new capabilities for TSMC V0.5 16-nm FinFET process layout design rules, device models, and electromigration and IR-drop (EM/IR) analysis. TSMC and Synopsys will continue to collaborate on certification of the Synopsys tool set until 16 nm FinFET reaches V1.0.

"TSMC works with Synopsys to ensure our customers have access to analog and mixed-signal design tools for TSMC's 16-nanometer FinFET process," said Suk Lee, senior director of design infrastructure marketing at TSMC. "The Custom Design Reference Flow is another milestone of the long term collaboration between the two companies."

TSMC and Synopsys Extend Custom Design Collaboration into 16 nm

Synopsys, Inc., a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced TSMC's certification of Synopsys' Laker custom design solution for the TSMC 16-nanometer (nm) FinFET process Design Rule Manual (DRM) V0.5 as well as the availability of a 16-nm interoperable process design kit (iPDK) from TSMC.

With its robust support for the iPDK standard, Synopsys' Laker custom design solution provides users with access to a wide range of TSMC process technologies, from 180-nm to 16-nm. Along with support for the TSMC 16-nm V0.5 iPDK, the Laker tool has been enhanced to enable full use of FinFET technology.

Synopsys and TSMC Enable Lithography Compliance Checking for 20 nm

Synopsys, Inc., a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced the delivery of lithography compliance checking technology for the TSMC 20-nanometer (nm) DFM Data Kit (DDK) encapsulated with Synopsys Proteus mask synthesis technologies. As a result of the design-for-manufacturing collaboration between TSMC and Synopsys, the compliance checking engine in the DDK helps designers identify lithography-related problems early in the design development phase, avoid litho-related manufacturing issues and late-stage schedule slips resulting from re-design.

The TSMC 20-nm DDK complements traditional physical verification rules with a highly accurate simulation-based solution to identify design non-compliance using a direct simulation of the manufacturing process. Lithography correction and verification tools used in the manufacturing mask synthesis flow are embedded in the DDK, resulting in accurate hotspot detection to avoid litho-related manufacturing issues.

Synopsys and TSMC Collaborate for 20 nm Reference Flow

Synopsys, Inc., a global leader accelerating innovation in the design, verification and manufacture of chips and systems, today announced 20-nanometer (nm) process technology support for the TSMC 20 nm Reference flow. This includes Synopsys Galaxy Implementation Platform support for the latest TSMC 20 nm design rules and models. The collaboration between TSMC and Synopsys on 20nm technology allows designers to gain performance, power efficiency and chip density advantages while achieving predictable design closure with the industry-proven Synopsys RTL to GDSII solution.

TSMC's 20 nm Reference Flow addresses 20 nm design challenges with a transparent double patterning aware design flow enabling double patterning technology (DPT) compliance, pre-coloring capability, new RC extraction methodology, DPT sign-off, and integrated design-for-manufacturing (DFM). The new Reference Flow's transparent DPT enablement reduces DPT design complexity, achieves required accuracy, minimizes 20 nm design flow setup and learning curve, and accelerates 20 nm process adoption.

AMD Selects Synopsys as a Verification IP Partner

Synopsys, Inc., a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced a multi-year agreement to provide Advanced Micro Devices, Inc. (AMD) with its next-generation Discovery Verification IP (VIP). Based on the new VIPER architecture, the recently announced Discovery VIP family provides inherent performance, ease-of-use and extensibility to speed and simplify verification of the most complex system-on-chip (SoC) designs. This agreement covers a variety of VIP titles including USB 3.0, ARM AMBA AXI interconnect, SATA 3.0, PCI Express Gen 3, and MIPI, as well as Synopsys' Protocol Analyzer, a unique protocol-aware SoC debug environment.

"In our verification environment for Southbridge SoCs and IP cores, we utilize several interfaces, including AXI3 and USB 3.0. After an extensive evaluation, we selected Synopsys' next-generation Discovery VIP for several of our leading SoC designs," said Thomas Bodmer, manager of design engineering at AMD. "With Discovery VIP, we have seen benefits in minimizing our simulation runs and achieving higher coverage. We have used Synopsys' Protocol Analyzer technology to narrow down protocol violations and debug the root causes."
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