Memory Controller

Here we compare the Venice's IMC with the one integrated into the Winchester. Used memory is TwinMOS Twister Pro with TCCD Chips. Samsung's TCCD Chips are known for their high clock rates and that they are able to run tight 2-2-2-5-7-256-1T timings at 200 MHz.
We reduced the multiplier on our 3800+, because we only had a 3200+ Winchester to compare to.

CPU Clock & Memory Ratio	Memory Speed	Memory Timings	Everest Read	Everest Write	Everest Latency
Winchester (3200+) 10 x 200 1:1	200 MHz	2-2-2-5 2.8V	5578 MB/s	2340 MB/s	47.2 ns
Venice (3200+) 10 x 200 1:1	200 MHz	2-2-2-5 2.8V	5369 MB/s	2393 MB/s	47.3 ns
Winchester (3000+) 9 x 200 1:1	200 MHz	2-2-2-5 2.8V	5419 MB/s	2290 MB/s	48.8 ns
Venice (3000+) 9 x 200 1:1	200 MHz	2-2-2-5 2.8V	5126 MB/s	2306 MB/s	49.3 ns

The Winchester has a higher read bandwith. Actually we expected a different picture, because we thought that the Venice has an improved Memory Controller. This does not seem to be the case.

Now we tried to find out what the maximum clock speeds are at relaxed 2.5-4-4-5-7-256-1T timings with 2.8V Vdimm. To make sure that the CPU's overclocking limits to do not hinder our test, we set the multiplier to 8 and Vcore to 1.5v.

CPU Clock & Memory Ratio	Memory Speed	Memory Timings	Everest Read	Everest Write	Everest Latency
Winchester 8 x 305 1:1	305 MHz	2,5-4-4-5 2.8V	7041 MB/s	3225 MB/s	43.0 ns
Venice 8 x 308 1:1	308 MHz	2,5-4-4-5 2.8V	6622 MB/s	3237 MB/s	42.6 ns

You can see a small advantage of 3 MHz. We do not know, if this is random luck or caused by the Venice core.

We saw no issues running four 512 MB modules (double sided) at 200 MHz with timings of 2.5-2-2-7 (Crucial Ballistix Tracer PC4000), but on both CPUs only with a CommandRate of 2T.

We could not find any advantage of the "new" memory controller in the Venice. That's a bit dissapointing. AMD could have certainly improved things, for example run 4x512MB at 1T.