AMD HD 5800 Series Leak Collection

Architecture

AMD sticks to its simplified GPU design model it calls TeraScale 2 architecture. Schematics show its SIMD engines to nucleate the GPU, surrounded by command and dispatch processors on one side (that intercept inputs from the host), raster operation engines on the other, and a hub that connects to the various I/O components such as the PCI-Express 2.0 interface, six-link display controllers, CrossFire Bridge Interconnect (CFBI), and UVD 2 video processors.





What is interesting to see is that to accommodate 1600 stream processors in 20 blocks of 80 each, the engineers branched out two groups of 10 blocks each, to make them best fit in the space. Both these "super-blocks" have their own interpolators, setup engines, and are connected to crossbars on both the dispatch and export fronts. Instructions per clock-cycle have also been improved over the previous generation. It's over to the slides for the rest.




AMD has also reworked their Anisotropic Filtering algorithm to provide near-perfect results at any angle.