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Crucial P5 500 GB

500 GB
Capacity
DM01B2
Controller
TLC
Flash
PCIe 3.0 x4
Interface
M.2 2280
Form Factor
Front
Back
Back
Package
Package
PCB Front
TweakTown
PCB Front
DRAM
TweakTown
DRAM
Flash
TweakTown
Flash
SSD Controller
Controller
NAND Die
NAND Die
The Crucial P5 is a solid-state drive in the M.2 2280 form factor, launched on April 21st, 2020. It is available in capacities ranging from 250 GB to 2 TB. This page reports specifications for the 500 GB variant. With the rest of the system, the Crucial P5 interfaces using a PCI-Express 3.0 x4 connection. The SSD controller is the DM01B2 from Micron, a DRAM cache chip is available. Crucial has installed 96-layer TLC NAND flash on the P5, the flash chips are made by Micron. To improve write speeds, a pseudo-SLC cache is used, so bursts of incoming writes are handled more quickly. The P5 is rated for sequential read speeds of up to 3,400 MB/s and 3,000 MB/s write; random IO reaches 210K IOPS for read and 500K for writes.
At its launch, the SSD was priced at 80 USD. The warranty length is set to five years, which is an excellent warranty period. Crucial guarantees an endurance rating of 300 TBW, a typical value for consumer SSDs.

Solid-State-Drive

Capacity: 500 GB
Variants: 250 GB 500 GB 1 TB 2 TB
Overprovisioning: 46.3 GB / 10.0 %
Production: Active
Released: Apr 21st, 2020
Price at Launch: 80 USD
Part Number: CT500P5SSD8
Market: Consumer

Physical

Form Factor: M.2 2280 (Single-Sided)
Interface: PCIe 3.0 x4
Protocol: NVMe 1.3
Power Draw: Unknown (Idle)
Unknown (Avg)
7.0 W (Max)

Controller

Manufacturer: Micron
Name: DM01B2
Architecture: ARM 32-bit Cortex R5 + M3
Core Count: 6-Core
Frequency: 700 MHz
Foundry: Micron
Flash Channels: 8 @ 1,200 MT/s
Chip Enables: 4
Controller Features: DRAM (enabled)

NAND Flash

Manufacturer: Micron
Name: B27A FortisFlash
Part Number: NW972
Rebranded: MT29F2T08EQHBFG8-R:B
Type: TLC
Technology: 96-layer
Speed: 50 MT/s .. 800 MT/s
Capacity: 2 chips @ 2 Tbit
ONFI: 4.0
Topology: Floating Gate
Die Size: 82 mm²
(6.2 Gbit/mm²)
Dies per Chip: 4 dies @ 512 Gbit
Planes per Die: 4
Decks per Die: 2
Word Lines: 106 per NAND String
90.6% Vertical Efficiency
Read Time (tR): 88 µs
Program Time (tProg): 800 µs
Block Erase Time (tBERS): 15 ms
Die Read Speed: 727 MB/s
Die Write Speed: 80 MB/s
Endurance:
(up to)		 2000 P/E Cycles
(40000 in SLC Mode)
Page Size: 16 KB
Block Size: 5184 Pages
Plane Size: 236 Blocks

DRAM Cache

Type: LPDDR4-2133
Name: MT53D512M16D1DS-046 IT:D (FBGA: D9ZCM)
Capacity: 1024 MB
(1x 1024 MB)
Organization: 8Gx16
Host-Memory-Buffer (HMB): N/A

Performance

Sequential Read: 3,400 MB/s
Sequential Write: 3,000 MB/s
Random Read: 210,000 IOPS
Random Write: 500,000 IOPS
Endurance: 300 TBW
Warranty: 5 Years
MTBF: 1.8 Million Hours
Drive Writes Per Day (DWPD): 0.3
SLC Write Cache: Yes

Features

TRIM: Yes
SMART: Yes
Power Loss Protection: No
Encryption:
  • AES-256
  • TCG Opal
RGB Lighting: No
PS5 Compatible: No

Reviews

Notes

Drive:

Crucial's P5 pSLC Cache it's not just Dynamic, it's adaptive, that means it works a bit different than most regular pSLC Cache implementations.
In this case it can increase in size up to 33% of the drive total capacity depending on how heavy the workload is.
And also, instead of just reprogramming the flash back to TLC, it retains parts of both OS and User Data in portions of the pSLC Cache for read resquest, by doing that and changing it's size it can optimize Write Amplification and performance.
And it also recover it's allocated space quite quickly.

Controller:

This controller uses 2 main cores using Cortex R5 clocked between 500 MHz - 700 MHz for NAND Management.
And 4 extra cores for predictable tasks and better efficiency offloading tasks from the main cores, using Cortex M3 cores clocked at ~ 200 MHz.
It might be 4 chip enable command per Channel, could be higher.
Jun 1st, 2024 05:40 EDT change timezone

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