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Neo Forza NFP455 4 TB

4 TB
Capacity
IG5236
Controller
TLC
Flash
PCIe 4.0 x4
Interface
M.2 2280
Form Factor
Front
SSD Controller
Controller
NAND Die
NAND Die
The Neo Forza NFP455 is a solid-state drive in the M.2 2280 form factor, launched in 2021. It is available in capacities ranging from 1 TB to 4 TB. This page reports specifications for the 4 TB variant. With the rest of the system, the Neo Forza NFP455 interfaces using a PCI-Express 4.0 x4 connection. The SSD controller is the IG5236 (Rainier) from InnoGrit, a DRAM cache chip is available. Neo Forza has installed 128-layer TLC NAND flash on the NFP455, the flash chips are made by YMTC. To improve write speeds, a pseudo-SLC cache is used, so bursts of incoming writes are absorbed more quickly. Copying data out of the SLC cache (folding) completes at 1000 MB/s. Thanks to support for the fast PCI-Express 4.0 interface, performance is excellent. The NFP455 is rated for sequential read speeds of up to 7,400 MB/s and 5,300 MB/s write; random IO reaches 600K IOPS for read and 900K for writes.
The SSD's price at launch is unknown. The warranty length is set to five years, which is an excellent warranty period. The TBW rating for the Neo Forza NFP455 4 TB is unknown, too.

Solid-State-Drive

Capacity: 4 TB (4000 GB)
Variants: 1 TB 2 TB 4 TB
Overprovisioning: 370.7 GB / 10.0 %
Production: Active
Released: 2021
Part Number: Unknown
Market: Consumer

Physical

Form Factor: M.2 2280 (Double-Sided)
Interface: PCIe 4.0 x4
Protocol: NVMe 1.4
Power Draw: Unknown

Controller

Manufacturer: InnoGrit
Name: IG5236 (Rainier)
Architecture: ARM 32-bit Cortex-R5
Core Count: Quad-Core
Frequency: 667 MHz
Foundry: TSMC FinFET
Process: 12 nm
Flash Channels: 8 @ 1,200 MT/s
Chip Enables: 4
Controller Features: DRAM (enabled)

NAND Flash

Manufacturer: YMTC
Name: Xtacking 2.0 (CDT1B)
Rebranded: (Rebranded)
Type: TLC
Technology: 128-layer
Speed: 1600 MT/s
Capacity: 4 chips @ 8 Tbit
ONFI: 4.1
Topology: Charge Trap
Die Size: 60 mm²
(8.5 Gbit/mm²)
Dies per Chip: 16 dies @ 512 Gbit
Planes per Die: 4
Decks per Die: 2
Word Lines: 141 per NAND String
90.8% Vertical Efficiency
Read Time (tR): 50 µs
Program Time (tProg): 620 µs
Block Erase Time (tBERS): 20 ms
Die Read Speed: 1280 MB/s
Die Write Speed: 70 MB/s
Endurance:
(up to)		 3000 P/E Cycles
Page Size: 16 KB
Block Size: 2304 Pages
Plane Size: 1980 Blocks

DRAM Cache

Type: DDR4
Capacity: Unknown

Performance

Sequential Read: 7,400 MB/s
Sequential Write: 5,300 MB/s
Random Read: 600,000 IOPS
Random Write: 900,000 IOPS
Endurance: Unknown
Warranty: 5 Years
SLC Write Cache: Yes
Cache Folding Speed: 1000 MB/s

Features

TRIM: Yes
SMART: Yes
Power Loss Protection: No
Encryption:
  • Unknown
RGB Lighting: No
PS5 Compatible: Yes

Notes

NAND Die:

Read Time (tR): Maximum is 50 µs, typical is lower
Typical Program Time (tPROG): 620 µs
Maximum Program Time (tPROG): Maximum is 910 µs
Block Erase Time (tBERS): Maximum is 20 ms, typical is lower
Array Eficiency of over 92%
YMTC 128L Xtacking 2.0 cell architecture consists of two decks connected through deck-interface buffer layer which is the same process with KIOXIA 112L BiCS 3D NAND structure. Cell size, CSL pitch, and 9-hole VC layouts keep the same design and dimension (horizontal/vertical WL and BL pitches) with previous 64L Xtacking 1.0 cell. Total number of gates is 141 (141T) including selectors and dummy WLs for the TLC operation.
This layout has a 1x 4 Plane layout, each one lineup side by side
Jun 1st, 2024 03:10 EDT change timezone

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