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Solidigm D7-5430 15 TB

15 TB
Capacity
Unknown
Controller
pQLC (PLC)
Flash
PCIe 4.0 x4
Interface
U.2
Form Factor
Front
PCB Front
PCB Front
PCB Back
PCB Back
NAND Die
NAND Die
The Solidigm D7-5430 is a solid-state drive in the U.2 form factor, launched on May 16th, 2023. It is only available in the 15 TB capacity listed on this page. With the rest of the system, the Solidigm D7-5430 interfaces using a PCI-Express 4.0 x4 connection. The actual SSD controller chip used it unknown, we'll update this page when we find out more. , a DRAM cache chip is available. Solidigm has installed 192-layer pQLC (PLC) NAND flash on the D7-5430, the flash chips are made by Intel. Thanks to support for the fast PCI-Express 4.0 interface, performance is excellent. The D7-5430 is rated for sequential read speeds of up to 7,000 MB/s and 3,000 MB/s write; random IOPS reach up to 935K for reads and 120K for writes.
The SSD's price at launch is unknown. The warranty length is set to five years, which is an excellent warranty period. Solidigm guarantees an endurance rating of 14300 TBW, a good value.

Solid-State-Drive

Capacity: 15 TB (15360 GB)
Overprovisioning: 2078.9 GB / 14.5 %
Production: Active
Released: May 16th, 2023
Part Number: SBFPF2BU153T00
Market: Enterprise

Physical

Form Factor: U.2
Interface: PCIe 4.0 x4
Protocol: NVMe 1.4
Power Draw: Unknown

Controller

Model: Unknown

NAND Flash

Manufacturer: Intel
Name: N4PA Q5171A
Type: pQLC (PLC)
Technology: 192-layer
Speed: 1600 MT/s
Capacity: Unknown
Topology: Floating Gate
Die Size: 73 mm²
(18.2 Gbit/mm²)
Planes per Die: 4
Decks per Die: 4
Endurance:
(up to)		 3000 P/E Cycles
(250000 in SLC Mode)
Page Size: 16 KB

DRAM Cache

Type: DDR4-3200
Name: SK Hynix
Capacity: 20480 MB
(10x 2048 MB)

Performance

Sequential Read: 7,000 MB/s
Sequential Write: 3,000 MB/s
Random Read: 935,000 IOPS
Random Write: 120,000 IOPS
Endurance: 14300 TBW
Warranty: 5 Years
MTBF: 2.0 Million Hours
Drive Writes Per Day (DWPD): 0.5
Write Cache: N/A

Features

TRIM: Yes
SMART: Yes
Power Loss Protection: Yes
Encryption:
  • AES-256
RGB Lighting: Unknown
PS5 Compatible: No

Notes

NAND Die:

Die read speed: aproximation
Die write speed: aproximation
In order to enable a balanced Gray data encoding, all five pages of data are needed in
both the first and second pass of the program algorithm. While this is the norm for most
QLC implementations except [1], it requires the storage of a few megabytes of data per
die in a DRAM or similar media. Instead, we use a 1b/cell (SLC) cache on the NAND die
to store the data needed for the two-pass PLC programming algorithm. To keep the area
overhead of the SLC cache to less than 2%, we improved the SLC reliability to 250k
program/erase (P/E) cycles, commensurate with 1k of P/E cycle capability in the present
PLC work.
Jun 1st, 2024 04:21 EDT change timezone

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