Thursday, November 12th 2009

AMD to Sample Bulldozer Architecture in 2010, Sets Product Priorities

As part of its Financial Analyst Day for 2009, AMD listed out its priorities for the year ahead, looking into 2010. While the company has lived up to its development targets for this year by releasing a full-fledged lineup of PC and server processors built on the 45 nm process, increasing its market share with graphics products, and releasing the first DirectX 11 compliant (back then referred to as 'next generation') GPU, the year ahead looks equally ambitious for AMD.

AMD set the following product priorities for 2010: to deliver four new winning PC platforms in the first half of 2010, improve battery life of its notebook platform, expand homegrown DirectCompute 11 and OpenCL developer tools, propagate DirectX 11 graphics to notebooks, launch the company's first 12-core Opteron processor, and more interestingly, sample the company's next-generation "Bulldozer" architecture to industry customers, along with sampling the company's first Fusion-design "Bobcat" processor, which integrates the CPU with GPU, along with sampling some of the company's first processors built on the 32 nm manufacturing process.

The four PC platforms AMD is referring to, are "Leo" and "Dorado", which succeed the current "Dragon" and "Pisces/Kodiak" as the new enthusiast and mainstream platforms, respectively. Leo brings with it the "Thuban" 6-core desktop processor, the company's 8-series platform core-logic, and DirectX 11 compliant discrete graphics, while "Dorado" continues to use Athlon II series processors with up to 4 cores, albeit on AMD's value 8-series core-logic (which continues to integrate DirectX 10.1 compliant IGP). It is in 2011, that processors up to 8 cores, based on the Bulldozer architecture, start to appear. AMD went as far as to disclose that the enthusiast-grade processor carrying the codename "Zambezi" will continue to come in the AM3 package, so now it is clear that the socket has a long road ahead. "Danube" and "Nile" are the other two platforms that AMD will introduce in H1, both are notebook platforms, which bring to the table support for up to 4 cores, DDR3 memory, and DirectX 10.1 compliant integrated, or DirectX 11 compliant discrete graphics, to the table.

Battery life is one of the biggest selling points of a notebook platform. It does not pay to have a powerful processor that is also power-hungry. AMD intends to bring the power footprint of its notebook platforms down by at least 25 percent. Backed with WHQL signed GPGPU drivers, AMD has already shown keen interest in GPGPU standards, particularly open standards such as Microsoft DirectCompute and OpenCL. It will keep this interest alive by continuing to make more developer tools and hardware optimizations in this area.

Propagating DirectX 11 graphics to notebooks is another priority, though it is not likely to come in the form of integrated graphics, going by the roadmap slides. With energy-effecient GPUs already developed across top market segments, it will only be a matter of designing mobile graphics boards. For the enterprise market, AMD will introduce its first 12-core processors codenamed "Magny Cours", and 6000/4000 series platforms. This is when AMD's own server core-logic re-enters the server market under a completely new design team. The core-logic will compete with offerings from NVIDIA and Broadcom.

Finally the one point that caught our interest is the one that AMD highlighted in its slide. AMD's next-generation processor architecture codenamed "Bulldozer", will start sampling in 2010. It should tell us that development of the architecture may have already commenced. Bulldozer is an architecture designed from ground up, and ideally, it does not inherit the design from its eight-year old K8 turned K10(.5) architecture. The other big development is that of the processor codenamed "Bobcat" that integrates graphics processing onto the processor package. It is unlikely to be the first of its kind, as rival Intel has already sampled such processors. It is in this year that AMD will also sample its first 32 nm processors, although no market availability of such processors is indicated.
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55 Comments on AMD to Sample Bulldozer Architecture in 2010, Sets Product Priorities

#2
pantherx12
If they were the best parties everyone would still be up by 4 in the morning!

That's when I used to go home from clubs and then party on boats until 9 am or so <_<
Posted on Reply
#3
wolf
Performance Enthusiast
pantherx12 said:
If they were the best parties everyone would still be up by 4 in the morning!

That's when I used to go home from clubs and then party on boats until 9 am or so <_<
Depends how early you start ;) and I always love a party cool enough for someone to get taped to the roof :laugh:

seriously I'm sidetracking badly here. sorry bta :o
Posted on Reply
#4
PP Mguire
I doubt bulldozer will be good enough to tear me away from my i5.
Posted on Reply
#5
eidairaman1
The Exiled Airman
TheLaughingMan said:
Not me because I don't know what a cylon is.
Battlestar Galactica (Ended)
Posted on Reply
#6
TheMailMan78
Big Member
eidairaman1 said:
Battlestar Galactica (Ended)
When I was a kid the only thing cooler looking than a Cylon were the tie fighter pilots.
Posted on Reply
#7
Kantastic
If this is new architecture from the ground up, I'd like to see it give Intel's HyperThreading a run for it's money. (Or pocket change.)
Posted on Reply
#8
eidairaman1
The Exiled Airman
Whats amazing is that is where the F-16 got its Nickname from, Pilots called it the Viper. Yet is the F-16: Fighting Falcon.
Posted on Reply
#10
mandis
I've learned not to expect much from amd these days.

I still think that amd's chips are of better quality and live longer than anything else on the market but this seems to be their only selling point these days...:ohwell:
Posted on Reply
#11
TheLaughingMan
mandis said:
I've learned not to expect much from amd these days.

I still think that amd's chips are of better quality and live longer than anything else on the market but this seems to be their only selling point these days...:ohwell:
And them being nice enough to ensure upgrade paths are simple and cheap. And their price/performance ratio.

I love how everyone just writes AMD off like the bastard, red-headed, step-child because they don't hold the absolute top spot in the performance charts.

Yes, Intel makes the fastest chips. Yes the i7 architecture is far ahead of AMD (except for games). But the K10 series and current stock of AM3 processors are leaps and bounds above the old Phenoms. Your 9950 even OC'ed to 3.2 is still handicapped compared to the Phenom II's. AMD is doing what they can do, improve their products with the resources available to them. Intel's R&D budget is probably higher than AMD entire corporate finance budget.
Posted on Reply
#12
vagxtr
Imsochobo said:
Phenom is basicly:
Improved HT
Improved Memory controller(added one aswell;) ) its dual 64 bit. not a single 128 bit if i got that right, something strange nonetheless.
Native Quadcore.
Improved IPC.
Support for Level 3 cache.
Over a A64 arch.

Maybe we'll see a New AMD juggernaut cpu from AMD, just like K7 K8 was :D
None of K8 architecture doesn't support HT (as Hyper Threading), and K8L or so called K10(.5) already get improved controller but AMD didnt resolve issues like broken half multi compatibility since K8 intro to first G1 late in 2006 (that's 3 fully years) and they build/test on that future of Phenom CPUs, and then they unganged memory so it could be accessed almost twice as faster with keeping latencies low like in real 128bit mode but that came at price when no easy OCing is possible since Phenom introduction cause no longer easy (for many claimed broken) CPU divider is used for memory frequency but now we have FSB multis like 1/2, 3/5 .... which makes memory always run at max even in PowerNow mode active. Well with detached MC with their own voltage control that doesnt have any affect except extra memory and mch consumption when CPU running in power saving mode and not really needing all of that memory bandwidth. They needed to implement PN for MCH too ;)

IPC isn't much improved in Phenoms (K8L) over old Athlon64 they just get capability to crunch whole 128b SSE in one cycle and got ability to handle much larger pages (needed for server application where lies amd 95% design orientation since K8 introduction) and that's pretty much it. L3 came as quick solution for never developed unified L2 like Intel did in their Core 2 architecture and looking forward to what Intels Nehalems would look like all in one development and cutting r&d budget they never had. And as far as ipc improvement goes more of them was done by ViA in latest Isaiah iteration than AMD has done for it's ipc in the last three years well maybe even 4 after they implemented SSE3 in E3 Venice core :wtf:

Bulldozer came out from realK10 development which is scraped down somewhere in 2006 and K9 was scraped year or two earlier. So they in fact look what IBM want for their server needs and looking on Sun's Niagara with already some job done in K10. What they really did in K9/K10 was never disclosed. Maybe that memory unganging came from one of that devs. Anyway K10 since it's first glimpses should have been a wholly revamped architecture, as Bulldozer should be, with only virtual support for old x86. And Bulldozer has that x86 nativlly implemented? Anyway HT in bd should resemble MHT like in Niagara (hence all that river codenames in amds bulldozer based server cpus :D:D) not some QuasiSMT like Intel didi in past and latest Atom/Nealem iterations. Again feature needed for server market in architecture that should serve them for next 10 years??? As K7-K8-K8L redesign did.
Posted on Reply
#13
btarunr
Editor & Senior Moderator
No, by HT he meant HyperTransport. Which indeed improved between K8 and K10. K10 used HyperTransport 3.0, with speeds between 1800 MHz (3.6 GT/s) and 2000 MHz (4.0 GT/s).

HyperThreading Technology is abbreviated as HTT.
Posted on Reply
#14
MrMilli
vagxtr said:
None of K8 architecture doesn't support HT (as Hyper Threading), and K8L or so called K10(.5) already get improved controller but AMD didnt resolve issues like broken half multi compatibility since K8 intro to first G1 late in 2006 (that's 3 fully years) and they build/test on that future of Phenom CPUs, and then they unganged memory so it could be accessed almost twice as faster with keeping latencies low like in real 128bit mode but that came at price when no easy OCing is possible since Phenom introduction cause no longer easy (for many claimed broken) CPU divider is used for memory frequency but now we have FSB multis like 1/2, 3/5 .... which makes memory always run at max even in PowerNow mode active. Well with detached MC with their own voltage control that doesnt have any affect except extra memory and mch consumption when CPU running in power saving mode and not really needing all of that memory bandwidth. They needed to implement PN for MCH too ;)

IPC isn't much improved in Phenoms (K8L) over old Athlon64 they just get capability to crunch whole 128b SSE in one cycle and got ability to handle much larger pages (needed for server application where lies amd 95% design orientation since K8 introduction) and that's pretty much it. L3 came as quick solution for never developed unified L2 like Intel did in their Core 2 architecture and looking forward to what Intels Nehalems would look like all in one development and cutting r&d budget they never had. And as far as ipc improvement goes more of them was done by ViA in latest Isaiah iteration than AMD has done for it's ipc in the last three years well maybe even 4 after they implemented SSE3 in E3 Venice core :wtf:

Bulldozer came out from realK10 development which is scraped down somewhere in 2006 and K9 was scraped year or two earlier. So they in fact look what IBM want for their server needs and looking on Sun's Niagara with already some job done in K10. What they really did in K9/K10 was never disclosed. Maybe that memory unganging came from one of that devs. Anyway K10 since it's first glimpses should have been a wholly revamped architecture, as Bulldozer should be, with only virtual support for old x86. And Bulldozer has that x86 nativlly implemented? Anyway HT in bd should resemble MHT like in Niagara (hence all that river codenames in amds bulldozer based server cpus :D:D) not some QuasiSMT like Intel didi in past and latest Atom/Nealem iterations. Again feature needed for server market in architecture that should serve them for next 10 years??? As K7-K8-K8L redesign did.
Biggest load of crap i've seen for a while .... :ohwell:
Posted on Reply
#15
vagxtr
btarunr said:
No, by HT he meant HyperTransport. Which indeed improved between K8 and K10. K10 used HyperTransport 3.0, with speeds between 1800 MHz (3.6 GT/s) and 2000 MHz (4.0 GT/s).

HyperThreading Technology is abbreviated as HTT.
Well Hyper Threading was first one using abb. HT ;) Just afterwards knowledge public asked for intel to differentiate themselves and in fact coining new abb HTT.

But what was i gonna ask is that on most places on the net we saw 2000MHz for HT3.0 (and 1000MHz for HT2.0 for the sake of reference) and adding to that as 4.0MT/s (and 2.0MT/s respectively). And thus gaining full bandwidth of 16GB/s (even in some official blogs. While most of more insight people use only 2.0MT/s x4bytes (2x 16bit lines) for HT3.0.

So i'd say i stand confused cause i know many of net advertisers use 2.0MT in HT2.0 just for the sake of marketing deliberately misleading people while it was just 1MT+1MT x16 bit or simply 1MT x2 x16bit and not in fact 2.0MT/s (reffering for HT2.0). So if you could clear out that misconceptions, especially in full XXGB/s bandwith in case of HT2.0 and now HT3.0.


MrMilli said:
Biggest load of crap i've seen for a while .... :ohwell:
Could you been more thorough :rolleyes: and wash your hands before typing.
Posted on Reply
#16
Super XP
MrMilli said:
Bulldozer has been in development from before 2007 (my guess is even before 2006)!
While i don't know the exact date that AMD commenced work on Bulldozer, designing a CPU architecture from the ground up generally takes 5 to 6 years (add a year sampling to that).
It has been confirmed already that Bulldozer is a completely new design developed from the ground up.
You mean before 2004. I would say more like 2003 about the same time Intel was working Sandybridge.
Posted on Reply
#18
OneCool
Will they ever have a work around for Intels Hyper Threading?

That seems to be their big draw back ATM.
Posted on Reply
#19
PP Mguire
Yea, its called bringing back pure AMD power. They have gotten used to being known as 2nd best again. I hate that.
Posted on Reply
#20
TIGR
Ah bummer, I was hoping Bobcat was a GPGPU, but sounds like it's just AMD's equivalent to the i3s with integrated graphics. After Larrabee, wouldn't it be something to see AMD be the first to release a mainstream GPGPU?

And with ATI and all their work on OpenCL, why not?
Posted on Reply
#21
PP Mguire
Actually, itd be the replacement of the i5 661+.
Posted on Reply
#22
Melvis
Let the games begin :pimp:
Posted on Reply
#23
nt300
[I.R.A]_FBi said:
whats sandybridge
It's Intels upcoming cpu design to compere with bulldozer.
Melvis said:
Let the games begin :pimp:
Theres a reason why AMD choose Bulldozer for its upcoming core design :D I think they plan on Bulldozing a bigger CPU company in 2011:eek:
Posted on Reply
#24
Melvis
nt300 said:

Theres a reason why AMD choose Bulldozer for its upcoming core design :D I think they plan on Bulldozing a bigger CPU company in 2011:eek:
Yea they have been wanting to do this for awhile now. Ive been following it as much as i can since they first said about Bulldozer, just hope it does as well as they say it will do.
Posted on Reply
#25
a_ump
so yea, bulldozer "sounds" awesome but so did phenom before release. But ima give AMD the benefit of the doubt, i have high expectations and think AMD will deliver with bulldozer. Also, did anyone else read that Anandtech article bout bulldozer's implementation of Multi-threading? From what i got amd is going to use a better method than what intel's HTT but its going to cost die space.
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