Friday, March 17th 2017

AMD Ryzen Infinity Fabric Ticks at Memory Speed

Memory clock speeds will go a long way in improving the performance of an AMD Ryzen processor, according to new information by the company, which reveals that Infinity Fabric, the high-bandwidth interconnect used to connect the two quad-core complexes (CCXs) on 6-core and 8-core Ryzen processors with other uncore components, such as the PCIe root-complex, and the integrated southbridge; is synced with the memory clock. AMD made this revelation in a response to a question posed by Reddit user CataclysmZA.

Infinity Fabric, a successor to HyperTransport, is AMD's latest interconnect technology that connects the various components on the Ryzen "Summit Ridge" processor, and on the upcoming "Vega" GPU family. According to AMD, it is a 256-bit wide bi-directional crossbar. Think of it as town-square for the chip, where tagged data and instructions change hands between the various components. Within the CCX, the L3 cache performs some inter-core connectivity. The speed of the Infinity Fabric crossbar on a "Summit Ridge" Ryzen processor is determined by the memory clock. When paired with DDR4-2133 memory, for example, the crossbar ticks at 1066 MHz (SDR, actual clock). Using faster memory, according to AMD, hence has a direct impact on the bandwidth of this interconnect.
Source: CataclysmZA on Reddit
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95 Comments on AMD Ryzen Infinity Fabric Ticks at Memory Speed

#52
Particle
ratirt
Yeah right. Forgot it is dual channel DDR.
Thanks for clarification. Well then in this case the only thing is to get the memory with higher frequency although I'm wondering now if it is worth additional money? Will this better performing memory really make noticeable difference. From a consumer stand point this difference should be noticeable if you wanna go with good 3200Mhz mem. Otherwise it's pointless.
It doesn't have anything to do with being dual channel. A DDR4-3200 module isn't named for its physical clock speed but rather its transaction rate. The link between the module and memory controller uses DDR signalling, meaning each data line toggles out two data bits for each cycle of the master clock. The master clock for the module is 1600 MHz (real).

The memory ICs on the DIMM itself run at an even lower clock speed. In this example, is it 300 MHz. DDR4 links at 4x the IC clock. DDR3 also links at 4x the IC clock. DDR2 links at 2x the IC clock. DDR links at 1x the IC clock. The underlying memory chips don't get much faster over time. Mostly they just get more dense.
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#53
papupepo
bug
Parallel programming is not extremely difficult. In fact, it can be fairly easy to do (look at Erlang or Go's goroutines). But most of the time it is more tedious to write and harder to test/maintain.
Caching has nothing to do with multi-threading. Caching is there to avoid memory read/writes, it doesn't actually care whether the CPU is running 1 or 1,000 threads.
L1 and L2 caches are always split and I know of no one trying to write multithreaded code in order not to upset L1 and L2 caches. If anything, that's a compiler's or a scheduler's job. I don't see why things would be any different when we're talking about L3 cache.
Like I said, we should learn about cache coherency. When data is shared by multiple cores, if a core update the data, the other cores must be immediately notified and the caches of the cores must be invalidated.
When data are shared by multiple CCX, the cost is very high. When data are shared by the cores on one CCX, or on a Intel processor, the cost is much lower, but it's still costly. So you shouldn't update shared data carelessly. You should create an update thread and put tasks on it. This can't be done by any scheduler or compiler.
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#54
Nebulous
Aenra
@nem.. dude how many more threads are you going to post that in? We got it :)
@Aenra He's multi-threaded, although his OS seems to have copy/paste issues :)
Posted on Reply
#55
bug
papupepo
Like I said, we should learn about cache coherency. When data is shared by multiple cores, if a core update the data, the other cores must be immediately notified and the caches of the cores must be invalidated.
When data are shared by multiple CCX, the cost is very high. When data are shared by the cores on one CCX, or on a Intel processor, the cost is much lower, but it's still costly. So you shouldn't update shared data carelessly. You should create an update thread and put tasks on it. This can't be done by any scheduler or compiler.
You might want to read this: https://arstechnica.com/gadgets/2017/03/intel-still-beats-ryzen-at-games-but-how-much-does-it-matter/
It touches on how developers feel about optimizing for each and every CPU, but there's more interesting stuff in there.
Posted on Reply
#56
Super XP
Legacy-ZA
This is the only thing I don't like what I read about the Ryzen CPU's.

Is there room for improvement? Yep. Will it cost you a new motherboard and CPU in the near future? Yep.
Nope, Socket AM4 is guaranteed to remain as the main socket up to at least mid to late 2019, when AMD transitions to Socket AM4+ via ZEN 3. So ZEN 1, ZEN 1+ and ZEN 2 are all based on Socket AM4. And ZEN 3 will be based on Socket AM4+ but will be backwards compatible with AM4, same scenario I would assume with AM3 & AM3+. This going by there Road Maps.

bug
You might want to read this: https://arstechnica.com/gadgets/2017/03/intel-still-beats-ryzen-at-games-but-how-much-does-it-matter/
It touches on how developers feel about optimizing for each and every CPU, but there's more interesting stuff in there.
I haven't read the link yet, but seeing AMD's strategy, they are making it easy to optimize and develop around there Architecture, both the CPU & GPU. AMD wants to push Multi-Threading as much as possible, and now Dev's have the ammunition to do such a thing. Will this catch on? I hope so, we've been stuck with Single Threading for far too long, and 4-Core setups should have been dumped in the garbage by now.
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#57
cdawall
where the hell are my stars
Super XP
Nope, Socket AM4 is guaranteed to remain as the main socket up to at least mid to late 2019, when AMD transitions to Socket AM4+ via ZEN 3. So ZEN 1, ZEN 1+ and ZEN 2 are all based on Socket AM4. And ZEN 3 will be based on Socket AM4+ but will be backwards compatible with AM4, same scenario I would assume with AM3 & AM3+. This going by there Road Maps.
Using terms like "guaranteed" in the PC world is never the best plan. AMD road maps have changed so many times it is honestly laughable to quote them as a truth. AMD will use whatever socket allows them to make the most money. If they end up with a massive change to design over the next couple of years or need to add additional PCI-e lanes expect that to change.
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#58
Super XP
cdawall
Using terms like "guaranteed" in the PC world is never the best plan. AMD road maps have changed so many times it is honestly laughable to quote them as a truth. AMD will use whatever socket allows them to make the most money. If they end up with a massive change to design over the next couple of years or need to add additional PCI-e lanes expect that to change.
I fully agree with your post. I am just going by what AMD said on National Television. When they launched Socket AM4 and Ryzen. They pretty much promised to keep AM4 for as long as possible.
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#59
cdawall
where the hell are my stars
Super XP
I fully agree with your post. I am just going by what AMD said on National Television. When they launched Socket AM4 and Ryzen. They pretty much promised to keep AM4 for as long as possible.
They also said on national TV that Bulldozer was the way of the future and performed better than anything intel had ever produced.
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#60
newtekie1
Semi-Retired Folder
Hmm... Kind of makes me wonder if this "Infinity Fabric" would go unstable with faster RAM. I mean, AMD recommends 3200 and 3500MT/s RAM, so the Infinity Fabric is running at 1600/1750MHz. But what about 4000MT/s RAM? That would put the Infinity Fabric running at 2000MHz. Will it be stable at that speed? If we push the RAM further?

Yes, I realize memory speeds that high are not supported, and AFAIK you can't actually even select memory speeds that high yet. But I'm thinking of the future. Is this interconnect going to become a limitation to memory speed down the road. If they have problems getting the interconnect stable at higher speeds, we might be limited to 3500MT/s memory in the future, which would suck.
Posted on Reply
#61
erek
newtekie1
Hmm... Kind of makes me wonder if this "Infinity Fabric" would go unstable with faster RAM. I mean, AMD recommends 3200 and 3500MT/s RAM, so the Infinity Fabric is running at 1600/1750MHz. But what about 4000MT/s RAM? That would put the Infinity Fabric running at 2000MHz. Will it be stable at that speed? If we push the RAM further?

Yes, I realize memory speeds that high are not supported, and AFAIK you can't actually even select memory speeds that high yet. But I'm thinking of the future. Is this interconnect going to become a limitation to memory speed down the road. If they have problems getting the interconnect stable at higher speeds, we might be limited to 3500MT/s memory in the future, which would suck.
is there any Multiplier settings that impact Infinity Fabric? Also what about Voltage settings?
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#62
Super XP
All is know is Infinity Fabric scales at the same speed as DDR4 Ram. The faster the Ram the better performance. AMD said they are working to increase RAM speed support as much as possible.
I don't see why Infinity Fabric Would become unstable at faster speeds.
Infinity Fabric Has a 256-Bit Quad Channel interface. Or a Bi directional channel. Something like that lok
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#63
newtekie1
Semi-Retired Folder
erek
is there any Multiplier settings that impact Infinity Fabric? Also what about Voltage settings?
As far as I can tell, there is no multiplier settings for the Infinity Fabric. It is just 1:1 with the memory speed. But That might change in the future. I don't know what voltage settings affect it either, but there might be the option to adjust its voltage.

Super XP
The faster the Ram the better performance. AMD said they are working to increase RAM speed support as much as possible.
I don't see why Infinity Fabric Would become unstable at faster speeds.
You very well might have answered your own question. They need to work on added faster RAM support because the Infinity Fabric is becoming unstable at the faster speeds.

Increasing clock speed on something always runs at the risk of it becoming unstable.
Posted on Reply
#64
Scrizz
Hood
So, the gist of this thread is, Ryzen should have been designed like an Intel CPU, with more memory channels, a monolithic core design, and a more capable IMC. Of course, it would cost more to make (just like Intel). So let's just make Ryzen into a clone of Intel's HEDT chips, and at the same price level. But hey, at least we can put on an AMD case badge, to let everyone know how much we hate Intel...
That's the same vibe I'm getting. :laugh::toast::nutkick:
Posted on Reply
#65
erek
Scrizz
That's the same vibe I'm getting. :laugh::toast::nutkick:
Can't they just make it so we can disable an entire CCX module without losing memory channels and L3 cache? Why can't they just release a Ryzen 4-core that's a single CCX module... bet it would OC well, and also not suffer the horrible restrictions of the Infinite Fabric.... seriously it's really nutso that the 1500X is configured to be 2x 2-core CCX modules and not a single 4-core CCX module:kookoo::kookoo::kookoo:
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#66
cdawall
where the hell are my stars
erek
Can't they just make it so we can disable an entire CCX module without losing memory channels and L3 cache? Why can't they just release a Ryzen 4-core that's a single CCX module... bet it would OC well, and also not suffer the horrible restrictions of the Infinite Fabric.... seriously it's really nutso that the 1500X is configured to be 2x 2-core CCX modules and not a single 4-core CCX module:kookoo::kookoo::kookoo:
That should leave it with a 16MB L3 instead of an 8MB. I would imagine in the future we will see an "athlon" style product using a single CCX
Posted on Reply
#67
newtekie1
Semi-Retired Folder
erek
Can't they just make it so we can disable an entire CCX module without losing memory channels and L3 cache? Why can't they just release a Ryzen 4-core that's a single CCX module... bet it would OC well, and also not suffer the horrible restrictions of the Infinite Fabric.... seriously it's really nutso that the 1500X is configured to be 2x 2-core CCX modules and not a single 4-core CCX module:kookoo::kookoo::kookoo:
The L3 cache is part of the CCX, so you can't disable a CCX and keep all the L3 cache.

But I guarantee we will see a 4-core that is just a single CCX. The CCX has no affect on memory channels, the memory controller is not part of the CCX.
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#68
Super XP
Yes the Ryzen 3 is a Quad Core. 8threads coming soon.

I read somewhere that AMD is going to release an update to enable a higher DDR4 multiplier to increase the RAM speed, hence increasing the Infinity Fabric.
Posted on Reply
#69
erek
Super XP
Yes the Ryzen 3 is a Quad Core. 8threads coming soon.

I read somewhere that AMD is going to release an update to enable a higher DDR4 multiplier to increase the RAM speed, hence increasing the Infinity Fabric.
I want a full-bore (1800X-style) single module 4-core CCX chip to totally do away with Infinite Fabric interconnect across cores. It is my thinking that such a chip could OC very well, and perform better in gaming without dealing with the Infinite Fabric bus in terms of core interconnect.
Posted on Reply
#70
newtekie1
Semi-Retired Folder
Super XP
Yes the Ryzen 3 is a Quad Core. 8threads coming soon.

I read somewhere that AMD is going to release an update to enable a higher DDR4 multiplier to increase the RAM speed, hence increasing the Infinity Fabric.
I can almost guarantee the first batch of the Ryzen Quad-Cores will be 8 core chips with 4 cores disabled, 2 cores from each CCX disabled.

Eventually they will release the single CCX 4 cores, probably with a model number bump to something like R3 1250X or something instead of the 1200X.
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#71
erek
newtekie1
I can almost guarantee the first batch of the Ryzen Quad-Cores will be 8 core chips with 4 cores disabled, 2 cores from each CCX disabled.

Eventually they will release the single CCX 4 cores, probably with a model number bump to something like R3 1250X or something instead of the 1200X.
Pretty sad about 2x 2-core CCX modules to make up a 4-core :( Just want rid of Infinite Fabric slowness / limitations :(
Posted on Reply
#72
cdawall
where the hell are my stars
erek
Pretty sad about 2x 2-core CCX modules to make up a 4-core :( Just want rid of Infinite Fabric slowness / limitations :(
Why would AMD not try to capitalize on half dead CCX's? It also gives customers a 16MB L3 cache on a quad core.
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#73
cadaveca
My name is Dave
cdawall
Why would AMD not try to capitalize on half dead CCX's? It also gives customers a 16MB L3 cache on a quad core.
Look at the die shots and you'll know why that won't happen. 8 MB, maybe, 16 MB? Not very likely. It is almost as though it is 8x 2 MB, when you look at the die shots.
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#74
cdawall
where the hell are my stars
cadaveca
Look at the die shots and you'll know why that won't happen. 8 MB, maybe, 16 MB? Not very likely. It is almost as though it is 8x 2 MB, when you look at the die shots.
The spec charts list full cache for the quads still? I mean they are prerelease, but still.
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#75
bug
cdawall
The spec charts list full cache for the quads still? I mean they are prerelease, but still.
Think about it: even if the whole L3 cache was left in there, the only way to address it would be over InfinityFabric. Same as reading from RAM.
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