A report from DigiTimes pits NAND manufacturers as accelerating their 120/128 layer 3D NAND technologies, aiming for volume production as early as 2020. Even as SK Hynix has begun sampling its 96-layer 4D NAND flash in March, Toshiba and Western Digital already had plans to introduce 128-layer technology, built on a TLC (Triple Level Cell) process technology so as to increase density while avoiding yield issues present with current QLC (Quad Level Cell) implementations.

The decision to accelerate deployment of the next generation of NAND comes from the fact that the market still faces an oversupply of NAND flash, mostly driven by the mature process of 64-layer NAND technology. With new technologies, higher ASPs and lower production scales are sustainable, which should enable supply to reduce enough so as to increase pricing of NAND-based technologies - and allow manufacturers to somewhat reset asking prices for new NAND chips.