Wednesday, August 12th 2020

Intel "Tiger Lake" Leverages 10 nm+ SuperFin and SuperMIM Technologies

Intel's upcoming 11th Generation Core "Tiger Lake" processors introduce the company's first major refinement of its 10 nanometer silicon fabrication node, dubbed 10 nm+. The node introduces two key features that work to improve the power characteristics of the silicon, allowing Intel to yield more performance without raising power/thermals over the previous generation. VideoCardz scored a major scoop on 10 nm+, including the introduction of the new SuperFin transistor, and SuperMIM capacitor.

SuperFin is a redesigned FinFET, a nanoscale transistor, which offers increased gate pitch, yielding higher drive current, improved channel mobility, and an improved source/drain, yielding in lower resistance. The other key component of 10 nm+ is SuperMIM, delivering a 5 times increase in metal-insulator-metal capacitance. Intel is yet to put out energy efficiency gain numbers for the process, but promises a "dramatic increase in frequency" over the previous generation, which lines up with leaks of the Core i7-1185G7 shipping with significantly higher clock speeds.
In related news, the "Willow Cove" CPU cores powering "Tiger Lake" reportedly features 1280 KB of L2 cache per core, a dramatic increase over the 512 KB of the "Sunny Cove" core, and 256 KB of the "Skylake" core (in ringbus-based dies). It also features a host of silicon level hardening against return/jump-based side-channel attacks. Its integrated memory controller supports LPDDR5-5400, LPDDR4X-4767, and dual-channel DDR4-3200 memory. The top trim of the Xe Gen12 iGPU solution features 96 execution units, and a dedicated 3840 KB L3 cache.

Intel technology chief architect and SVP Raja Koduri is expected to detail all of the innovations that go into "Tiger Lake," at a virtual press-event on August 13.
Sources: VideoCardz, Raja Koduri (Twitter)
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27 Comments on Intel "Tiger Lake" Leverages 10 nm+ SuperFin and SuperMIM Technologies

#1
dj-electric
I see someone got tomorrow's presentation.
Pluses may or may not be completely gone from future branding and PR btw. Intel may or may not be fed up with people pointing at a long line of pluses and laugh.
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#2
Vya Domus
That's a ridiculous amount of L2 cache, these are rather desperate measures to claw back some performance in synthetic tests. Plus caches are expensive and consume a lot of power, both of which are undesirable traits in a mobile chip. And they claim more clock speed, which means even more power consumption.
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#3
Axaion
More cache, nice.

Not holding my breath on when its getting released to consumers can buy them though..
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#4
Assimilator
Vya Domus
That's a ridiculous amount of L2 cache, these are rather desperate measures to claw back some performance in synthetic tests. Plus caches are expensive and consume a lot of power, both of which are undesirable traits in a mobile chip. And they claim more clock speed, which means even more power consumption.
Speculation based on months of these rumours: Willow Cove is designed to handle variable amounts of cache. Higher-end and desktop SKUs will get more, mobile parts less. The values quoted would likely represent the highest-end configuration (HEDT/server).

And bigger caches are not just for show or benchmark, they're critical for preventing trips to main memory, which is one of the major factors in CPU performance. They are definitely going to be expensive though (in terms of cost, heat, power, and die area).
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#5
Vya Domus
Assimilator
And bigger caches are not just for show or benchmark, they're critical for preventing trips to main memory, which is one of the major factors in CPU performance.
Bigger caches are worth it only when the access pastern is sequential/regular. That happens a lot in synthetic tests, in real world applications though not as much. A desktop Ryzen chip has what, almost 70mb in total of cache ? Doesn't make that much of a difference.
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#6
Bruno Vieira
Dear intel, benchmarks and power consumption figures is all people care about, zen2 and renoir is showing that.
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#7
laszlo
i think soon ....The Empire Strikes Back...
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#9
AsRock
TPU addict
dj-electric
I see someone got tomorrow's presentation.
Pluses may or may not be completely gone from future branding and PR btw. Intel may or may not be fed up with people pointing at a long line of pluses and laugh.
I hope he don't drop it.
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#10
BorisDG
Nothing new for the cache. My Cascade Lake-X has 1024MB L2 per core. Idk if matthers tho.
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#11
phanbuey
Vya Domus
Bigger caches are worth it only when the access pastern is sequential/regular. That happens a lot in synthetic tests, in real world applications though not as much. A desktop Ryzen chip has what, almost 70mb in total of cache ? Doesn't make that much of a difference.
It does help quite a bit in games too since it minimizes the cache miss delays to an extent. There is definitely a point of diminishing returns though.
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#12
Vayra86
Yet more Lake yadayada and yet no product on shelves.
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#13
ShurikN
Missed opportunity to call it 10nm SuperMEME
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#14
randomUser
We're still like 2-3 years away from seeing 10nm CPUs in mainstream. And they started talking about 10nm+ already.
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#15
efikkan
Vya Domus
That's a ridiculous amount of L2 cache, these are rather desperate measures to claw back some performance in synthetic tests. Plus caches are expensive and consume a lot of power, both of which are undesirable traits in a mobile chip.
Larger caches improve several aspects of performance, not only limited to cache misses etc. It also helps data intensive AVX workloads like video encoding.
I don't believe caches use that much power compared to ALUs, FPUs, etc.

If it yields a reasonable performance increase for the die space and other trade-offs, then I'm all for it, no matter how "desperate" you think it is.
Vya Domus
Bigger caches are worth it only when the access pastern is sequential/regular. That happens a lot in synthetic tests, in real world applications though not as much. A desktop Ryzen chip has what, almost 70mb in total of cache ? Doesn't make that much of a difference.
There is a huge difference between L2 and L3 cache in access patterns. L3 cache is also a overflow cache, while the prefetcher feeds into L2, and each cache line in L2 is probably >10x as "useful" as each one in L3.

Cache is also a lot more than just size, there is latency, associativity, bandwidth etc.
Vayra86
Yet more Lake yadayada and yet no product on shelves.
Ice Lake-U is shipping in large quantities. Tiger Lake will too.
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#16
Tom Yum
As I suspected. One the areas where people have been pointing to in support of the argument Intel 10nm = TSMC 7nm is gate pitch. If 10nm+ increases gate pitch to support more drive current (hence faster switching), then effectively Intel are trading density for performance. Which is fine, but underscores that a workable, high performance Intel 10nm process is more like TSMC 10nm and that they are further behind TSMC than previously thought. This is what Intel have been doing with 14nm revisions to eek more clock speed as well, which is why those process comparisons have always been BS.
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#17
HugsNotDrugs
Cache is expensive in terms of die size and power consumption. When Intel is more than doubling cache and including very capable iGPUs you know the day as come where competition exists.

Having said all that the Tiger Lake CPUs look really good with that healthy IPC lift.
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#18
hellrazor
How long has Intel been stuck trying to rice out their process node?
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#19
tygrus
Does Intel maths mean that 10+1=11?
Intel 10nm = TSMC 7nm
Intel 10nm+ = Intel 11nm = TSMC 8nm
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#20
Flanker
ShurikN
Missed opportunity to call it 10nm SuperMEME
More like SuperLATE
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#21
watzupken
I observed an increasing usage of the word Super of late. I wonder what is so super about it. Till we see the end product, this remains another marketing gimmick in my opinion. Good thing they did not call this AvengersFin and AvengersMIM.
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#22
RandallFlagg
laszlo
i think soon ....The Empire Strikes Back...
And the amount of butthurt denial here at TPU will be staggering.
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#23
voltage
dj-electric
I see someone got tomorrow's presentation.
Pluses may or may not be completely gone from future branding and PR btw. Intel may or may not be fed up with people pointing at a long line of pluses and laugh.
oddly amd does the same, but the fan boys dont bitch, but those same people like to complain about intel like little brats. its infantile.
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#24
Octopuss
I had no idea Intel had 10nm.
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#25
Assimilator
Here we go: www.anandtech.com/show/15971/intels-11th-gen-core-tiger-lake-soc-detailed-superfin-willow-cove-and-xelp
dj-electric
Pluses may or may not be completely gone from future branding and PR btw. Intel may or may not be fed up with people pointing at a long line of pluses and laugh.
Yup, 10nm++ is now "10SF" (SuperFin). 10nm+++ will be 10ESF (Enhanced SuperFin). Time to retire those plus memes.

This incarnation of Tiger Lake is a mobile-focused 4-core (presumably 8-thread) design.
Uses Willow Cove cores which are essentially the same as Sunny Cove.
Performance is supposedly up 10 - 20% over Ice Lake but this is due entirely to 10SF allowing clocks up to 5GHz again, as opposed to the maximum 4GHz on Ice Lake/10nm+.
PCIe 4.0 is supported but only via 4 lanes due to power consumption concerns; higher core count versions of TGL (for desktop) will have more lanes.
Power is ~15W compared to 7700HQ (also 4c/8t) at 45W - third of the power draw with integrated Thunderbolt 4/USB 4/PCIe 4.0 is not too shabby.

The new integrated Xe graphics are mostly irrelevant, but have hardware AV1 support and quad 4K outputs. Discrete Xe parts are apparently being fabbed at a third party.

Overall, interesting, but not very exciting - especially for desktop users.
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