Monday, May 16th 2022

AMD Ryzen 7000 "Phoenix" APUs with RDNA3 Graphics to Rock Large 3D V-Cache

AMD's next-generation Ryzen 7000-series "Phoenix" mobile processors are all the rage these days. Bound for 2023, these chips feature a powerful iGPU based on the RDNA3 graphics architecture, with performance allegedly rivaling that of a GeForce RTX 3060 Laptop GPU—a popular performance-segment discrete GPU. What's more, AMD is also taking a swing at Intel in the CPU core-count game, by giving "Phoenix" a large number of "Zen 4" CPU cores. The secret ingredient pushing this combo, however, is a large cache.

AMD has used large caches to good effect both on its "Zen 3" processors, such as the Ryzen 7 5800X3D, where they're called 3D Vertical Cache (3D V-cache); as well as its Radeon RX 6000 discrete GPUs, where they're called Infinity Cache. The only known difference between the two is that the latter is fully on-die, while the former is stacked on top of existing silicon IP. It's being reported now, that "Phoenix" will indeed feature a stacked 3D V-cache.
The exact function of this isn't known—whether it serves as a last-level cache for the CPU or iGPU. AMD's APU architecture differs from Intel's processors that have iGPUs. On the Intel chips, the L3 cache serves as town-square for the entire SoC, with each IP block contributing an L3 cache slice that make up a functionally-contiguous cache that all IP blocks can equally address over the Ring Bus. On AMD APUs such as "Cezanne" or "Rembrandt," the L3 cache is part of the CCX (CPU cores complex), and serves exclusively as last-level cache for the CPU cores. The iGPU has its own LLC, and the Infinity Fabric interconnect is the ether binding all IP blocks on the silicon.

The obvious direction for development in future APUs could be a unification of last-level cache for the CCX and iGPU, provided the cache is large enough for the function—and this can be accomplished by stacked cache. An RDNA2 GPU with performance rivaling the RTX 3060 Laptop GPU, the Radeon RX 6650M XT, based on the "Navi 23" silicon, has 32 MB of Infinity Cache. This means, with some clever cache memory-management, an LLC size in the neighborhood of 64 MB could emerge feasible for the APU.
Source: Greymon55 (Twitter)
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45 Comments on AMD Ryzen 7000 "Phoenix" APUs with RDNA3 Graphics to Rock Large 3D V-Cache

#1
Rhein7
Woa this could kill some low end GPUs, and at the same time becoming a fast gaming CPU too if you add faster GPU later.
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#2
Count von Schwalbe
If this stuff ends up in desktop processors too, there would be little reason to buy a GPU under $200 for whole-system upgrades.
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#3
ExplodingCaps
Damn, this is insane. Then, you don't need fast ram if you can fit everything inside massive cache!
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#4
Chaitanya
This could be interesting, hopefully 7000 series doesnt suffer the same latency related performance requirements of AM4 CPUs.
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#5
R0H1T
Rhein7Woa this could kill some low end GPUs, and at the same time becoming a fast gaming CPU too if you add faster GPU later.
AMD's not launching this unless they plan to abandon the sub $150-200 dGPU market. Remember that 5900x 3D chip, yeah me neither :laugh:

This thing's gonna be expensive & unless they plan to use 3d cache for Ryzen 3 or below, not really a great alternative to combo of cheap (old?) dGPU & non IGP Ryzen 3 chips!
ExplodingCapsdon't need fast ram
Fast RAM always helps, though I'd argue more (dense) RAM is better than expensive fast RAM.
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#6
Count von Schwalbe
R0H1TAMD's not launching this unless they plan to abandon the sub $150-200 dGPU market. Remember that 5900x 3D chip, yeah me neither :laugh:
Bear in mind that this is the laptop market, which Ryzen is rare in, and Radeon is worse. Looks like AMD is pulling all stops to gain market share.
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#7
btarunr
Editor & Senior Moderator
Count von SchwalbeBear in mind that this is the laptop market, which Ryzen is rare in, and Radeon is worse. Looks like AMD is pulling all stops to gain market share.
I don't think 22.5% is all that rare. 1 in 5 laptops shipped in Q1-2022 had an AMD processor. Almost 1 in 4.
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#8
R0H1T
Count von SchwalbeBear in mind that this is the laptop market, which Ryzen is rare in, and Radeon is worse. Looks like AMD is pulling all stops to gain market share.
Yes I missed that, but the point about pricing remains. 5800x 3D is expensive because of yields as well, that thing is harder to make & is more "fragile" apparently!
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#9
Crackong
Are we going to see 192MB cache on a consumer class CPU?
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#10
AusWolf
Before we all start binning our 3060s and 6600s, I must ask: what about RAM bandwidth as a bottleneck?
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#11
Minus Infinity
AusWolfBefore we all start binning our 3060s and 6600s, I must ask: what about RAM bandwidth as a bottleneck?
Run you 3060 at 60W and see how it performs. That's the level of performance Phoenix is targetting, not a desktop unfettered 3060.
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#12
Mussels
Freshwater Moderator
AusWolfBefore we all start binning our 3060s and 6600s, I must ask: what about RAM bandwidth as a bottleneck?
DDR5 is gunna smash that higher than we're used to, combining the higher bandwidth with the lower latency from the cache should be a real winner of a design
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#13
InVasMani
So guess my presumptions were right about RDNA3 and 3D stacked cache on APU. I can't wait to see AMD transition towards incorporating Xilinx FPGA IP into their designs as well both with and without CPU's or GPU's since it can be integrated with either option together or all three combined. I'm keen to see what role 3D stacked cache will have with FPGA's as well. From what we've seen of the cache thus far it bodes well for power efficiency so that could help add to the overall appeal of FPGA's. Really interesting times ahead for technology across a lot of different fields of tech.
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#14
Tigger
I'm the only one
If they can get enough supply from TSMC
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#15
Mats
R0H1TYes I missed that, but the point about pricing remains. 5800x 3D is expensive because of yields as well, that thing is harder to make & is more "fragile" apparently!
You missed the important part that those 5800X3D chiplets could have have gone into crazy expensive Milan-X EPYC CPU's, so there's quite a bit of internal competition going on.

The 16 core 7373X is the slowest and the most insane model, with 8 chiplets, but only 2 cores active on each chiplet, for $4200. So, 75 % of all cores disabled, just to get 48 MB L3 cache per core.. I wouldn't be surprised if it's a typo. The 24 core is cheaper lol.



The Phoenix is single chip and pretty much can't end up anywhere else than in the reasonably priced consumer/client space.
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#16
AnarchoPrimitiv
Large cache might be the "fix" for APUs in solving the memery issue
InVasManiSo guess my presumptions were right about RDNA3 and 3D stacked cache on APU. I can't wait to see AMD transition towards incorporating Xilinx FPGA IP into their designs as well both with and without CPU's or GPU's since it can be integrated with either option together or all three combined. I'm keen to see what role 3D stacked cache will have with FPGA's as well. From what we've seen of the cache thus far it bodes well for power efficiency so that could help add to the overall appeal of FPGA's. Really interesting times ahead for technology across a lot of different fields of tech.
Yes, I'm also very interested in seeing what AMD can do with Xilinix IP, probably some insane semi-custom SoCs at the least, but who knows, perhaps dedicated chiplets in a package for certain tasks
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#17
Valantar
This is really interesting, and I hope it pans out. I also hope they've taken stacking into consideration from the start of the design, i.e. not just making this into a cache die stacked on top, but rather a cache+I/O die below what is either a single CPU+GPU die or two discrete ones. Given the thermal constraints of mobile implementations this is the only sensible approach IMO - and bringing the I/O into the bottom cache die would bypass a lot of the problems of sticking a die beneath a CPU die. If they've made it so the top die only needs IF links and power circuitry, that would drastically lower the need for TSVs passing through the bottom die (essentially only requiring power vias).
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#18
Vayra86
Man AMD"s long term tech investments are really coming to fruition now. Let's hope they shake that lower end GPU market up and kill discrete altogether in the segment.
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#19
InVasMani
TiggerIf they can get enough supply from TSMC
That statement pretty well holds true of damn near the entire tech industry however.
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#20
AnarchoPrimitiv
R0H1TAMD's not launching this unless they plan to abandon the sub $150-200 dGPU market. Remember that 5900x 3D chip, yeah me neither :laugh:

This thing's gonna be expensive & unless they plan to use 3d cache for Ryzen 3 or below, not really a great alternative to combo of cheap (old?) dGPU & non IGP Ryzen 3 chips!


Fast RAM always helps, though I'd argue more (dense) RAM is better than expensive fast RAM.
If they scale up volume of 3d cache, it should bring the price down, and if an APU allows you to reach 3060 performance, it will warrant the price... I could see SFF pre-built going nuts over this
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#21
Tigger
I'm the only one
InVasManiThat statement pretty well holds true of damn near the entire tech industry however.
Still true in this regard though
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#22
Valantar
AnarchoPrimitivIf they scale up volume of 3d cache, it should bring the price down, and if an APU allows you to reach 3060 performance, it will warrant the price... I could see SFF pre-built going nuts over this
Yeah, the 5800X3D is clearly an experiement, and while there's no doubt the extra die area needed for a large cache has a cost, as does the new packaging method, it doesn't need to be massive, and can bring significant savings with it if the product stack is fundamentally designed around stacking. Separating I/O and cache into a base die (PCIe, RAM, IF for top-stacked compute dice, maybe media encode/decode if it fits + the cache) with stripped-down CPU and GPU dice on top would make those more complex top dice smaller and easier to produce in volume, which would bring down costs and improve yields - especially when compared to large-ish APU dice. It would also add a ton of implementation flexibility, allowing for larger or smaller silicon to be stacked on top for a wider range of parts with the same general platform capabilities. There's a lot of potential in these types of packaging - it just depends how things align with AMD's design cycles, fab and packaging availability, etc.
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#23
Durvelle27
R0H1TYes I missed that, but the point about pricing remains. 5800x 3D is expensive because of yields as well, that thing is harder to make & is more "fragile" apparently!
I find this funny because the 5800X3D is not expensive. It's a new product with the same MSRP as the last gen 5800X :roll:
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#24
mechtech
Judging from the mark up on the 5800x3d I’d say make the run of the mill for me so I can save $100.

unless the price difference is going to be $20 ish
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#25
Aquinus
Resident Wat-man
MatsYou missed the important part that those 5800X3D chiplets could have have gone into crazy expensive Milan-X EPYC CPU's, so there's quite a bit of internal competition going on.

The 16 core 7373X is the slowest and the most insane model, with 8 chiplets, but only 2 cores active on each chiplet, for $4200. So, 75 % of all cores disabled, just to get 48 MB L3 cache per core.. I wouldn't be surprised if it's a typo. The 24 core is cheaper lol.



The Phoenix is single chip and pretty much can't end up anywhere else than in the reasonably priced consumer/client space.
Go look over at Phoronix and you'll be astonished at how much an improvement that 768MB of LLC on those EPYC chips makes. It's pretty amazing to be honest.
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Jun 25th, 2022 23:14 EDT change timezone

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