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[VR-Zone]DirectX 11 screens...

InnocentCriminal

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... I'm sceptical at the best of times so I'm calling BS on these screens, but I thought it might bring up a decent debate.











Not out of the realms of possiblity, but these pictures, I highly doubt these are screens for a DX11 demo (with some clever dick behind the keyboard I wouldn't be surprised if this sort of thing could be done in DX10.1 or even 9) - I'd like to be proven wrong though.

Source.
 
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LOL this is a joke right?
 

DaC

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Assuming FSX 10 ss hoax..... this is totally BS
 

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Fake, I've seen these pictures somewhere else, and they are related to ray tracing. I remember the industry/microsoft deciding DX11 wasn't going to go Ray Tracing~ so yeah I call hoax.
 

DaMulta

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I don't call it BS.


look when Shader 2.0 was around total thread length was 96. Then when Shader 3.0 came out it went to 64000 maximum length That's a big deal correct?

Well it would be buy only 2 games really pushed the limit then. FEAR a 2.0 game, and Far Cry a 3.0 game. Both look about the same, because the thread length was pushed more.

The average game then had 19-25 length threads the majority of the time.

Now we have sharder 4.0 and it is supposed to have no limit. Does that mean that they will use that?


As you can still see today only a few games really push the limit. When we should be seeing games like Futermark is showing off!!!!

Developers simply are catching a little bit at a time when we are doing all this upgrading. If they sat down and just focused on something cool based on one GPU they could pull some amazing things off. Just like they do on the 360......
 

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Who gives a f***k. Like DX 10 bullshit the best looking game is DX9 Crysis.
The whole point of DX10 was its efficiency over DX9 but how come all games works slower at DX10 mode.
 

DaMulta

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Who gives a f***k. Like DX 10 bullshit the best looking game is DX9 Crysis.
The whole point of DX10 was its efficiency over DX9 but how come all games works slower at DX10 mode.

bad coding
 

InnocentCriminal

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I don't call it BS.


look when Shader 2.0 was around total thread length was 96. Then when Shader 3.0 came out it went to 64000 maximum length That's a big deal correct?

Well it would be buy only 2 games really pushed the limit then. FEAR a 2.0 game, and Far Cry a 3.0 game. Both look about the same, because the thread length was pushed more.

The average game then had 19-25 length threads the majority of the time.

Now we have sharder 4.0 and it is supposed to have no limit. Does that mean that they will use that?


As you can still see today only a few games really push the limit. When we should be seeing games like Futermark is showing off!!!!

Developers simply are catching a little bit at a time when we are doing all this upgrading. If they sat down and just focused on something cool based on one GPU they could pull some amazing things off. Just like they do on the 360......

Arrrh someone with an objective retort. Nice one dude! I'm only calling BS on these images being officially DX11 screens. I'm not saying DX11 won't look similar or have the same prowess, just look at Crysis in DX9 like r9 said.

You make a valid point though.
 

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i say bs. We aren't even near the processing power it would take to generate such random scenes.
 

DaMulta

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i say bs. We aren't even near the processing power it would take to generate such random scenes.

We are closer than you think we are.....


Everything today is coded horrible.

Just to use things you have to do this
A first-generation programming language is a machine-level programming language.

Second-generation programming language is a generational way to categorize assembly languages. The term was coined to provide a distinction from higher level third-generation programming languages (3GL) such as COBOL and earlier machine code languages. Second-generation programming languages have the following properties:

* The code can be read and written by a programmer. To run on a computer it must be converted into a machine readable form, a process called assembly.
* The language is specific to a particular processor family and environment.


A third-generation language (3GL) is a refinement of a second generation programming language. Where as a second generation language is more aimed to fix logical structure to the language, a third generation language aims to refine the usability of the language in such a way to make it more user friendly. This could mean restructuring categories of possible functions to make it more efficient, condensing the overall bulk of code via classes (eg. Visual Basic). In a Nutshell, a third generation language benefits over a second by having more refinement on the usability of the language itself from the perspective of the user.

A fourth-generation programming language (1970s-1990) (abbreviated 4GL) is a programming language or programming environment designed with a specific purpose in mind, such as the development of commercial business software[1]. In the evolution of computing, the 4GL followed the 3GL in an upward trend toward higher abstraction and statement power. The 4GL was followed by efforts to define and use a 5GL.

The natural-language, block-structured mode of the third-generation programming languages improved the process of software development. However, 3GL development methods can be slow and error-prone. It became clear that some applications could be developed more rapidly by adding a higher-level programming language and methodology which would generate the equivalent of very complicated 3GL instructions with fewer errors. In some senses, software engineering arose to handle 3GL development. 4GL and 5GL projects are more oriented toward problem solving and systems engineering.

All 4GLs are designed to reduce programming effort, the time it takes to develop software, and the cost of software development. They are not always successful in this task, sometimes resulting in inelegant and unmaintainable code. However, given the right problem, the use of an appropriate 4GL can be spectacularly successful as was seen with MARK-IV and MAPPER (see History Section, Santa Fe real-time tracking of their freight cars - the productivity gains were estimated to be 8 times over COBOL). The usability improvements obtained by some 4GLs (and their environment) allowed better exploration for heuristic solutions than did the 3GL.

A quantitative definition of 4GL has been set by Capers Jones, as part of his work on function point analysis. Jones defines the various generations of programming languages in terms of developer productivity, measured in function points per staff-month. A 4GL is defined as a language that supports 12 - 20 FP/SM. This correlates with about 16 - 27 lines of code per function point implemented in a 4GL.

Fourth-generation languages have often been compared to domain-specific programming languages (DSLs). Some researchers state that 4GLs are a sub-set of DSLs. [2] Given the persistence of assembly language even now in advanced development environments (MS Studio), one expects that a system ought to be a mixture of all the generations, with only very limited use of the first.

A fifth-generation programming language (abbreviated 5GL) is a programming language based around solving problems using constraints given to the program, rather than using an algorithm written by a programmer. Most constraint-based and logic programming languages and some declarative languages are fifth-generation languages.

While fourth-generation programming languages are designed to build specific programs, fifth-generation languages are designed to make the computer solve the problem for you. This way, the programmer only needs to worry about what problems need to be solved and what conditions need to be met, without worrying about how to implement a routine or algorithm to solve them. Fifth-generation languages are used mainly in artificial intelligence research. Prolog, OPS5, and Mercury are the best known fifth-generation languages.

These types of languages were also built upon Lisp, many originating on the Lisp machine. ICAD is a good example. Then, there are many frame languages, such as KL-ONE.

Operating modes

[edit] Real mode

Main article: Real mode

Real mode is an operating mode of 80286 and later x86-compatible CPUs. Real mode is characterized by a 20 bit segmented memory address space (meaning that only 1 MB of memory can be addressed), direct software access to BIOS routines and peripheral hardware, and no concept of memory protection or multitasking at the hardware level. All x86 CPUs in the 80286 series and later start up in real mode at power-on; 80186 CPUs and earlier had only one operational mode, which is equivalent to real mode in later chips.

In order to use more than 64 KB of memory, the segment registers must be used. This created great complications for C compiler implementors who introduced odd pointer modes such as "near", "far" and "huge" to leverage the implicit nature of segmented architecture to different degrees, with some pointers containing 16-bit offsets within implied segments and other pointers containing segment addresses and offsets within segments.

[edit] Protected mode

Main article: Protected mode

In addition to real mode, the Intel 80286 supports protected mode, expanding addressable physical memory to 16 MB and addressable virtual memory to 1 GB, and providing protected memory, which prevents programs from corrupting one another. This is done by using the segment registers only for storing an index to a segment table. There were two such tables, the Global Descriptor Table (GDT) and the Local Descriptor Table (LDT), each holding up to 8192 segment descriptors, each segment giving access to 64 KB of memory. The segment table provided a 24-bit base address, which can be added to the desired offset to create an absolute address. Each segment can be assigned one of four ring levels used for hardware-based computer security.

The Intel 80386 introduced support in protected mode for paging, a mechanism making it possible to use virtual memory.

Paging and segmented memory access are required for modern multitasking operating systems. Linux, 386BSD and Windows NT were developed for the 386 because it was the first Intel architecture CPU to support paging and 32-bit segment offsets. The 386 architecture became the basis of all further development in the x86 series. The success of Windows 3.0, the first widely accepted version of Microsoft Windows, was largely due to its ability to take advantage of 386 features, even though it was used mainly to run multiple sessions rather than to take advantage of the native 32-bit instruction set.

x86 processors that support protected mode boot into real mode for backward compatibility with the older 8086 class of processors. Upon power-on (aka booting), the processor initiates itself into Real mode, and then it begins loading programs automatically into RAM from ROM and disk. A program inserted somewhere along the boot sequence may be used to put the processor into the Protected mode. The instruction set in protected mode is backward compatible with the one used in real mode.

[edit] Virtual 8086 mode

Further information: Virtual 8086 mode

There is also a sub-mode of operation in 32-bit Protected mode, called virtual 8086 mode. This is basically a special hybrid operating mode that allows real mode programs and operating systems to run while under the control of a Protected mode supervisor operating system. This allows for a great deal of flexibility in running both Protected mode programs and real mode programs simultaneously. This mode is available in the 32-bit version of Protected mode; virtual 8086 mode does not exist previously in the 16-bit version of Protected mode, or in the 64-bit long mode.

[edit] 64-bit Long mode

Main article: Long mode

By 2002, it was obvious that the 32-bit address space of the x86 architecture was limiting its performance in applications requiring large data sets. A 32-bit address space would allow the processor to directly address only 4 GB of data, a size surpassed by applications such as video processing and database engines, while using the 64-bit address, one can directly address 16777216 TB (more than 17 billion GB) of data, although most 64-bit architectures don't support access to the full 64-bit address space (AMD64, for example, supports only 48 bits, split into 4 paging levels, from a 64-bit address).

AMD, who would traditionally follow the lead of Intel, took the initiative of extending the 32-bit x86 architecture to 64-bit, initially calling it x86-64, later renaming it AMD64. The Opteron, Athlon 64, Turion 64, and later Sempron families of processors use this architecture. The success of the AMD64 line of processors coupled with the lukewarm reception of the IA-64 architecture forced Intel to release their own x86-64 instruction set. Intel had previously developed an x86-64 instruction set[10] but opted not to enable it in hopes that AMD would not make it to market with theirs before Itanium's new IA-64 instruction set was widely adopted. They branded their extensions EM64T architecture, and later re-branded it Intel 64.

In its literature and product version names, Microsoft and Sun refer to AMD64/Intel 64 collectively as x64 in the Windows and Solaris operating systems respectively. Linux distributions refer to it either as "x86-64", its variant "x86_64", or "amd64". BSD systems use "amd64" while Mac OS X uses "x86_64".

Long mode is mostly an extension of the 32-bit instruction set, but unlike the 16–to–32-bit transition, many instructions were dropped in the 64 bit mode. This does not affect actual binary backward compatibility (which would execute legacy code in other modes that retain support for those instructions), but it changes the way assembler and compilers for new code have to work.

This was the first time that a major upgrade of the x86 architecture was initiated and originated by a manufacturer other than Intel. It was also the first time that Intel accepted technology of this nature from an outside source.

[edit] Extensions

[edit] Floating point unit

Further information: Floating point unit

Initially, IA-32 included floating-point capabilities only on add-on processors (8087, 80287 and 80387.) With the introduction of the 80486, these 8 80x87 floating point registers, known as ST(0) through ST(7) are built in to the CPU. Each register is 80 bits wide and stores numbers in the double extended precision format of the IEEE floating-point standard.

These registers are not accessible directly, but are accessible like a LIFO stack. The register numbers are not fixed, but are relative to the top of the stack; ST(0) is the top of the stack, ST(1) is the next register below the top of the stack, ST(2) is two below the top of the stack, etc. That means that data is always pushed down from the top of the stack, and operations are always done against the top of the stack. Register access had to be done in the stack order, not randomly.

[edit] MMX

Main article: MMX (instruction set)

MMX is a SIMD instruction set designed by Intel, introduced in 1997 for Pentium MMX microprocessors. It developed out of a similar unit first used on the Intel i860. It first appeared in the Pentium MMX. It is supported on most subsequent IA-32 processors by Intel and other vendors. MMX is typically used for video applications.

MMX added 8 new "registers" to the architecture, known as MM0 through MM7 (henceforth referred to as MMn). In reality, these new "registers" were just aliases for the existing x87 FPU stack registers. Hence, anything that was done to the floating point stack would also affect the MMX registers. Unlike the FP stack, these MMn registers were fixed, not relative, and therefore they were randomly accessible. The instruction set did not adopt the stack-like semantics so that existing operating systems could still correctly save and restore the register state when multitasking without modifications.

Each of the MMn registers are 64-bit integers. However, one of the main concepts of the MMX instruction set is the concept of packed data types, which means instead of using the whole register for a single 64-bit integer (quadword); two 32-bit integers (doubleword), four 16-bit integers (word) or eight 8-bit integers (byte) may be used. Also because the MMX's 64-bit MMn registers are aliased to the FPU stack, and each of the stack registers are 80-bit wide, the upper 16-bits of the stack registers go unused in MMX, and these bits are set to all ones, which makes it look like NaN's or infinities in the floating point view. This makes it easier to tell whether you are working on a floating point data or MMX data.

[edit] 3DNow!

Main article: 3DNow!

In 1997 AMD introduced 3DNow! The introduction of this technology coincided with the rise of 3D entertainment applications and was designed to improve the CPU's vector processing performance of graphic-intensive applications. 3D video game developers and 3D graphics hardware vendors use 3DNow! to enhance their performance on AMD's K6 and Athlon series of processors.

3DNow! was designed to be the natural evolution of MMX from integers to floating point. As such, it uses the exact same register naming convention as MMX, that is MM0 through MM7. The only difference is that instead of packing byte to quadword integers into these registers, one would pack single precision floating points into these registers. The advantage of aliasing registers with the FPU registers is that the same instruction and data structures used to save the state of the FPU registers can also be used to save 3DNow! register states. Thus no special modifications are required to be made to operating systems which would otherwise not know about.

[edit] SSE

Main articles: Streaming SIMD Extensions, SSE2, SSE3, SSSE3, SSE4, and SSE5

In 1999, Intel introduced the Streaming SIMD Extensions (SSE) instruction set, following in 2000 with SSE2. The first addition made MMX almost obsolete and the second allowed the instructions to be realistically targeted by conventional compilers. Introduced in 2004 along with the Prescott revision of the Pentium 4 processor, SSE3 added specific memory and thread-handling instructions to boost the performance of Intel's HyperThreading technology. AMD licensed the SSE3 instruction set and implemented most of the SSE3 instructions for its revision E and later Athlon 64 processors. The Athlon 64 does not support HyperThreading and lacks those SSE3 instructions used only for HyperThreading.

SSE discarded all legacy connections to the FPU stack. This also meant that this instruction set discarded all legacy connections to previous generations of SIMD instruction sets like MMX. But it freed the designers up, allowing them to use larger registers, not limited by the size of the FPU registers. The designers created eight 128-bit registers, named XMM0 through XMM7. (Note: in AMD64, the number of SSE XMM registers has been increased from 8 to 16.) However, the downside was that operating systems had to have an awareness of this new set of instructions in order to be able to save their register states. So Intel created a slightly modified version of Protected mode, called Enhanced mode which enables the usage of SSE instructions, whereas they stay disabled in regular Protected mode. An OS that is aware of SSE will activate Enhanced mode, whereas an unaware OS will only enter into traditional Protected mode.

SSE is a SIMD instruction set that works only on floating point values, like 3DNow!. However, unlike 3DNow! it severs all legacy connection to the FPU stack. Because it has larger registers than 3DNow!, SSE can pack twice the number of single precision floats into its registers. The original SSE was limited to only single-precision numbers, like 3DNow!. The SSE2 introduced the capability to pack double precision numbers too, which 3DNow! had no possibility of doing since a double precision number is 64-bit in size which would be the full size of a single 3DNow! MMn register. At 128-bit, the SSE XMMn registers could pack two double precision floats into one register. Thus SSE2 is much more suitable for scientific calculations than either SSE1 or 3DNow!, which were limited to only single precision. SSE3 does not introduce any additional registers.

[edit] Physical Address Extension (PAE)

Main article: Physical Address Extension

By default, physical addresses are 32-bit, however, there exists a page extension mode called Physical Address Extension or PAE, first added in the Intel Pentium Pro, which allows an additional 4 bits of physical addressing. The size of memory in Protected mode is usually limited to 4 GB. Through tricks in the processor's page and segment memory management systems, x86 operating systems may be able to access more than 32-bits of address space, even without the switchover to the 64-bit paradigm. This mode does not change the length of segment offsets or linear addresses; those are still only 32 bits.

[edit] Virtualization

x86 virtualization is difficult because the architecture did not meet the Popek and Goldberg requirements until recently. Nevertheless, there are several commercial x86 virtualization products, such as VMware, Parallels and Microsoft Virtual PC, as well as open source virtualization projects such as QEMU+KQEMU, VirtualBox, Xen. Other methods, such as the Kernel-based Virtual Machine ("KVM"), require newer processors which provide more hardware support for virtualization.[citation needed]

Intel and AMD have introduced x86 processors with hardware-based virtualization extensions that overcome the classical virtualization limitations of the x86 architecture. These extensions are known as Intel VT (IVT or simply VT) that was code named "Vanderpool," and AMD-V that was code named "Pacifica." Although most modern x86 server-based and many modern x86 desktop-based processors include these extensions, the technology is generally considered immature at this point with most software-based virtualization outperforming these extensions.[11] This is expected to change as the technology matures.



So do you get it?



There is a reason for our programs installing Gigs of information. It is because we build on top of another, and another, and another. We always reuse what there was before. We have never went back and did it all over again.

So you write the 101010101010 code
Then you right the ABCDEFG code
Then you right the code that can take ABCD and make new programs.
Then you take that new program and you build on this
It goes on
and
on
and
on
and
on

Each time it has to talk all the way down to 01010101011


Today if we dropped all our codes and went back to 010101010 it would be almost imposable to catch up to where we are. At the same time if we did, we would not use as much space, and we would not need the house power that we use to day to do the things that we do today.

Install windows 95 or nt on a 3Ghz Quad and just watch how fast it starts.

That is because there is less code to talk all the way down too 01010101011.


Video cards should have a driver written on the card, and when you kick in a game it should load the whole thing into ram. Then handle it all in assemble code. Then you would have the images above that you see.


All we do today, could of been done on computers 20 years ago. It just took longer to code than it does now, because most of the train tack has already been laid.
 
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I personally won't state my opinion of if I think they are real or not, but some looks amazing, and others look doable in DX10. Personally I'll just wait for now. Oh, and DaMulta, I think that is the longest post I've seen. :respect:
 

Wile E

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I personally won't state my opinion of if I think they are real or not, but some looks amazing, and others look doable in DX10. Personally I'll just wait for now. Oh, and DaMulta, I think that is the longest post I've seen. :respect:

If that's the longest post you've seen, you clearly weren't around for the APK days. lol.

At any rate, I think these screens are fake.
 

Solaris17

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Benchmark Scores I dont have time for that.
i think they could be real but maybe some rendered DX11 images at best imo...but i hold hope those are operating renderes man i hope DX11 looks like that TEHHHHH SEEXXXX
 

DaMulta

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Clearly you guys have not seen real tech demos where they push shit to the limit of what it can really do.
http://forums.techpowerup.com/showpost.php?p=1066650&postcount=5

I hope one of these days, you guys get to sit in front of a terminal too a supercomputer. Then run one of their demos that shows you what the supercomputer can render or not render for you.


In the earily 90s I see demos that would be judged against our best games to day. That was on a SGi computer that took the whole room up and only ran at 80Mhz.

They used to read computers in mips(million instructions per second). I wish they still did today because Ghz and Mhz is a stupid way to rate computer parts.


If I can send 10000000million things in 1Ghz and you can only send 5000 thousand things in 1Ghz.

Which one if faster?

Then tell me why we rate them in speed, and why we don't judge them on what they can do in a set amount of time.
 

James1991

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All i will say is if the first and last ones are real then stop making games that look like S**T and use the full potential of DirectX :rockout:
 

Wile E

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Clearly you guys have not seen real tech demos where they push shit to the limit of what it can really do.
http://forums.techpowerup.com/showpost.php?p=1066650&postcount=5

I hope one of these days, you guys get to sit in front of a terminal too a supercomputer. Then run one of their demos that shows you what the supercomputer can render or not render for you.


In the earily 90s I see demos that would be judged against our best games to day. That was on a SGi computer that took the whole room up and only ran at 80Mhz.

They used to read computers in mips(million instructions per second). I wish they still did today because Ghz and Mhz is a stupid way to rate computer parts.


If I can send 10000000million things in 1Ghz and you can only send 5000 thousand things in 1Ghz.

Which one if faster?

Then tell me why we rate them in speed than in what they can do in a set amount of time.
Most of us know what tech demos are. We are claiming this is not one of them.
 

Solaris17

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Clearly you guys have not seen real tech demos where they push shit to the limit of what it can really do.
http://forums.techpowerup.com/showpost.php?p=1066650&postcount=5

I hope one of these days, you guys get to sit in front of a terminal too a supercomputer. Then run one of their demos that shows you what the supercomputer can render or not render for you.


In the earily 90s I see demos that would be judged against our best games to day. That was on a SGi computer that took the whole room up and only ran at 80Mhz.

They used to read computers in mips(million instructions per second). I wish they still did today because Ghz and Mhz is a stupid way to rate computer parts.


Is I can send 10000000million things in 1Ghz and you can only send 5000 thousand things in 1Ghz.

Which one if faster?

Then tell me why we rate them in speed than in what they can do in a set amount of time.



i think your doubting alot of people and too much....for example other than the fact its by some random japanese web site i dont trust even if it is DX11 which imo is very probably you and i both know it will be a few years before our rigs can do it....i wouldnt go calling "i wish you guys" iv been inside unix farms were they use CPU clusters to render images and movies 1 frame at a time each frame taking hours because of how incredably precise it is and the images beautiful their is no doubt nor are people as stupid as you MAY think (not saying you think anyone is stupid) im just saying be a little more carefull i mean i took no offense but their are people like me that have seen this shit right up close others that have and do work at these places. and we have seen know and worked on thse things first hand im not doubting todays tech im doubting user end because some of that kind of stuff is locked so tight we wont see it in our TT armors or hack boxes for years to come.
 

DaMulta

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Most of us know what tech demos are. We are claiming this is not one of them.

I know that, but they could render those things.


The house alone is something they have been doing for years with Cad cards.
 

DaMulta

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i think your doubting alot of people and too much....for example other than the fact its by some random japanese web site i dont trust even if it is DX11 which imo is very probably you and i both know it will be a few years before our rigs can do it....i wouldnt go calling "i wish you guys" iv been inside unix farms were they use CPU clusters to render images and movies 1 frame at a time each frame taking hours because of how incredably precise it is and the images beautiful their is no doubt nor are people as stupid as you MAY think (not saying you think anyone is stupid) im just saying be a little more carefull i mean i took no offense but their are people like me that have seen this shit right up close others that have and do work at these places. and we have seen know and worked on thse things first hand im not doubting todays tech im doubting user end because some of that kind of stuff is locked so tight we wont see it in our TT armors or hack boxes for years to come.

I do doubt a lot, and there is a TON that I have no understanding of.

Most people do not know how things work on a basic level tho......that's true.

Sorry if I seem to be in a bad mood...........long long long day.
 

Wile E

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I know that, but they could render those things.


The house alone is something they have been doing for years with Cad cards.

Oh, I know. If it weren't possible to render, we wouldn't be seeing the images. The images alone prove it's possible for these to be rendered. i just don't happen to believe these are DX11 renders. I bet they are 3DsMax or similar.
 

Solaris17

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I do doubt a lot, and there is a TON that I have no understanding of.

Most people do not know how things work on a basic level tho......that's true.

Sorry if I seem to be in a bad mood...........long long long day.

i know dude and i understand i have a migrane im almost out of ciggs and my room is hot but i think before you diss you should try to give some credit i mean if you whanna talk sophisticated F intel and AMD sparcs are were its at i have an old box at my cousins house thats running solaris 10 8 cores 4 threads per core 32 logical threads 1Ghz operating frequncy its a niagra based Ultra sparc and that rig would destroy mainstream CPU's if normal OS's supported it..
 

DaMulta

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i know dude and i understand i have a migrane im almost out of ciggs and my room is hot but i think before you diss you should try to give some credit i mean if you whanna talk sophisticated F intel and AMD sparcs are were its at i have an old box at my cousins house thats running solaris 10 8 cores 4 threads per core 32 logical threads 1Ghz operating frequncy its a niagra based Ultra sparc and that rig would destroy mainstream CPU's if normal OS's supported it..

I have been awake for two days now lol

and went to work both days:slap:
 

Solaris17

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I have been awake for two days now lol

and went to work both days:slap:

ugh nthats rough you need fukitol good stuff

now go look at the "how you use your os" thread i want to know what you think of my multi tasking beacause i live through TPu's replies to me like a highschooler craving myspace.
 
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Real. These images were from Micosofts DX11 demo from a month or two ago. XNA Gamefest if I'm not mistaken.
 
Last edited:

Wile E

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Real. These images were from Micosofts DX11 demo from a month or two ago.

I still say they weren't rendered in DX11. I bet they are just concept renders. I remember the DX10 "renders" they posted before it released. Those renders never made it in a tech demo for some reason. Hmmmmmm.
 
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