Technically it's called the reference clock. It's not called HT, HT reference clock, FSB, HT bus or any of those things, just simply reference clock. It's like the base clock on the i series intel CPUs'. I researched this a while back.
Not quite
Core Speed = Reference Clock * CPU Multiplier
Northbridge Speed = Reference Clock * Northbridge Multiplier
HyperTransport Link Speed = Reference Clock * HyperTransport Multiplier
Et cetera.
For all intents and purposes, the reference clock is still the good old FSB
So, using my X4 965 as a very basic example:
Core Speed: 200MHz (FSB) * 17 (CPU's native multiplier) = 3400MHz
HT: 200MHz (FSB) * 10 (HT's native Link Speed multiplier) = 2000MHz (which translates to 4000MT/s (MegaTransfers/second)).
Et cetera.
Physically the CPU's memory controller still needs to communicate with the RAM, which is done over the FSB, which is why changing the HT/NB does not affect the FSB, but the HT/NB
are affected by a change in FSB.
This also explains why increasing the CPU's multiplier gives a greater through-put (bandwidth), than does raising the FSB to get to the same Clock Speed.
To see a simple demonstration of that, run IntelBurnTest, with the CPU @ 4GHz.
At 20x 200FSB, a 1920mb calculation will take
less than 55 seconds on the X4 965 (roughly 42 GFlops).
At 16x 250FSB, that same calculation will take
more than 55 seconds (roughly 40/41 GFlops).
Your mileage may vary, of course, but the disparity will be there.
I just used 4GHz as an example, as it's a relatively easy (..) to get speed on the X4 965. Use whichever speed you like; the effect is still the same regardless
The whole point of AMD utilising HT, is to remove the [potential/encountered] inadequacies that the FSB has with the modern architectures, which can cause bottlenecks and/or other slow-downs.
The way things are going, I can't imagine FSB disappearing completely in a fairly short time-frame.
It
is bound to be scrapped though.
BTW, HT is (a few technical exceptions aside) the same as Intel's QPI - both negate the need for many tasks that used to go through the FSB, hence the on-board memory controllers (thus including the NB) of the respective camps' CPUs.
Fascinating stuff
Edit:
This is what I remember from AMD's & the HyperTransport Consortium's respective white papers on the subject.
My memory is not as reliable as it used to be, which is why we have people like erocker & Kei, to name but a few, to help us steer through the murky waters
at that time my l3 and ram were reletively close in there perfromance numbers
