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Navi 21, 22 and 23 specs - TDP & Clocks

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This GPU would allegedly feature up to 80 Compute Units (5120 Stream Processors if each CU has 64 cores). The variant listed in macOS11 appears to have a boost clock at 2050 MHz with Navi 21A variant and up to 2200 MHz with Navi 21B variant.

With a boost clock of 2200 MHz, the Navi 21B would have a shader performance of 22.5 TFLOPs. For comparison, with NVIDIA’s new dual SM architecture, the GeForce RTX 3080 graphics card has a maximum FP32 throughput of 29.8 TFLOPs.

Navi 22 – Navy Flounder
The mid-tier GPU in a lineup appears to feature 40 CUs, so just as many as Navi 10. Therefore, the GPU is expected to be an RDNA2 version of mid-range graphics for the upcoming RX 6700 series. The GPU is listed with a (maximum) GPU clock of 2500 MHz, so even higher than Navi 21.

Navi 23 – Dimgrey Cavefish
The entry-level GPU called Navi 23 is also listed in the firmware. Judging from the data collected by the Reddit stblr, we can conclude that the full number of CUs is 32 (so around 2048 Stream Processors). The frequency charts are not featured in the firmware yet.

We can already say that AMD will gain in efficiency this time ?
 
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Why does that 40CU have to be the 6700 XT?
What if it's the 6600 XT ?
The segments don't make sense with it at 6700 XT
 

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The Radeon Pro 5600M in my laptop has 40 CUs. This doesn't seem to be outside of the realm of possibility.
Isn't that just AMD following Nvidia formula? Higher stream processor and lower clock speed.
 

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This indicates that navi 22 is the console class gpu in full configuration for xbox sx and Ps5 in cut down configuration just like Rx470/570 and Rx480/580 were to Ps4 pro and xbox one X, and need to be priced accordingly to be competitive against consoles.
 

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Isn't that just AMD following Nvidia formula? Higher stream processor and lower clock speed.
I think you have that backwards. AMD has traditionally done that. nVidia is really pushing it now though.
 
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Higher stream processor and lower clock speed.

That has always been the case since GPUs existed. You ideally want many processors at lower clock speeds because the power doesn't scale linearly.
 
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Why does that 40CU have to be the 6700 XT?
What if it's the 6600 XT ?
The segments don't make sense with it at 6700 XT
The biggest dies can yield 2 SKUs, the full die, and a smaller one cut down in order to improve yields. Also, the 40CU SKU can be clocked way higher than to lower bin 72 CU, so the distance in performance might be smaller than the CU count could lead you to believe. Anyway, it's still just a rumor.

I think you have that backwards. AMD has traditionally done that. nVidia is really pushing it now though.
When you have very big dies, you have to reduce clocks a bit, it's not about Nvidia or AMD, a 500 sq mm die will always have less overclocking headroom than a 300 one. And, indeed, Nvidia has been competing with very large dies since more than 10 years ago.

Well, this is still a rumor, but if it were true, the highest SKU should mop the floor with the 3080, provided there are no issues with memory bandwidth.
 
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The biggest dies can yield 2 SKUs, the full die, and a smaller one cut down in order to improve yields. Also, the 40CU SKU can be clocked way higher than to lower bin 72 CU, so the distance in performance might be smaller than the CU count could lead you to believe. Anyway, it's still just a rumor.


When you have very big dies, you have to reduce clocks a bit, it's not about Nvidia or AMD, a 500 sq mm die will always have less overclocking headroom than a 300 one. And, indeed, Nvidia has been competing with very large dies since more than 10 years ago.

Well, this is still a rumor, but if it were true, the highest SKU should mop the floor with the 3080, provided there are no issues with memory bandwidth.

That would put a 96CU as 6900 XT

interestingly I was having a look at the Rx 5300, 5300 XT and 5500 XT are all the same chip with different Memory and clock speed set up.
They're listed as the 5500 XT being 12% faster overall. Which seems to be about the clock speed differences for all them. One of these cards is 96 bit vs 128 Bit. after looking at that, the notion that this 256 bit isn't enough doesn't really seem like a complaint anymore.
 
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Is there a reason preventing gpus with it coming later than cpus? I mean what could be simpler, 4GHz signals or 1.5ghz signals trafficking over some mcm hub.

I want AMD to bring back custom driver antialiasing modes and this time rotated grid checkerboard patterned 200% resolution scaling to make entry. Couple it with edge detect z-buffer shader or what not and we are good to go.
 
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RDNA3 most probably.


I've never heard of any leak pointing to more than 80 CU and I find it very unlikely...

It was speculation on segmentation of where it could fit in.

Is there a reason preventing gpus with it coming later than cpus? I mean what could be simpler, 4GHz signals or 1.5ghz signals trafficking over some mcm hub.

I want AMD to bring back custom driver antialiasing modes and this time rotated grid checkerboard patterned 200% resolution scaling to make entry. Couple it with edge detect z-buffer shader or what not and we are good to go.

Infinity fabric is/has been scaled to work station cards with a link.

How ever it's a latency thing that everyone is worried about in GPU's with MCM, as with latency you won't want micro-stuttering.

I want the ability to change Crossfire and SLI rendering to Scissor and tile instead if always AFR
 
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How ever it's a latency thing that everyone is worried about in GPU's with MCM,
Gpus are already multicompartmental devices. There is a command processor which decodes stuff up ahead, I think. However, apart from that, everything down is pretty sectioned off. Do rasterizers trade pointers?
 
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The RDNA2 speculation thread on anandtech was talking about how RDNA2 will have bigger cache for supposedly overcoming the memory bandwidth related issues cause big navi is 256-bit and GDDR6 compred to rtx 3000's custom GDDR6X and wider bus. Some were saying bigger cache is also to prepare for next-gen MCM designs or sth. I don't have anandtech account so can anyone eli5?
 
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Gpus are already multicompartmental devices. There is a command processor which decodes stuff up ahead, I think. However, apart from that, everything down is pretty sectioned off. Do rasterizers trade pointers?

it's usually all inside a cache or scheduler the moment you go outside of those you hit some latency as you got farther way from the shader cores.

In all honest I don't like how everyone keeps saying multi-gpu is dead, and yet want M.C.M GPU's which are very similar to multi gpu in my view,

a L3 cache on the GPU could be beneficial if it's kept inside a central hub for synchronization of all chiplets.

I'm more along the thought that the central hub will be able to Just delete frames that came late.
 
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it's usually all inside a cache or scheduler the moment you go outside of those you hit some latency as you got farther way from the shader cores.
Well, I haven't thought about that. Scalar thread management requires access to the thread mask. It has to run in sync with the clock phase. Somewhere down the Polaris cycle, gpu latency took the center stage from gpu throughput. Now, developers don't develop for dispatch, they do it for the retire order. I hope we have more of their wonderful inventions, I love scalarization.
So, that is off the table. Maybe, they can mcm the compute units. You know they come with lds scratch memory that doesn't have to be so fast. I don't know. This stuff overwhelms me.

Or, they can make vector accesses through the mcm ports. Serial accesses need their own discrete buswidth, or they can access serially.
Is it harder than cpu mcm, though? Gpus don't run on coherency checks all the time. It could be a hardware rule to finish work in a serial fashion. We just caused ourselves a lot of problems. :)
It will still be wild when AMD launches this in consoles which I'm looking forward to with their crazy hardware setups. Each new launch is more exotic.
 
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Do rasterizers trade pointers?

Nope, it's all data independent, they don't even access shared memory within the CUs as far as I know. MCM GPUs will become a thing as soon as there is a need for them, the implementation is relatively "trivial".

In all honest I don't like how everyone keeps saying multi-gpu is dead, and yet want M.C.M GPU's which are very similar to multi gpu in my view,

Distributing work on chips on the same package is very different from distributing work across PCI-e devices. The difference in latency is orders of magnitude worse, not to mention the issues asymmetrical multiprocessing brings with it.

Multi-GPU for real time applications is dead and buried.
 
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The rumored massive caches are more or less inevitable at this point.
Yeah, well I remember that on launch day, AIB's had the number of CU completely wrong for Nvidia 30X0 GPUs, so I'm not ruling out last-minute changes, especially since there seem to be 2 controllers on these chips, one for GDDR6 and one for HBM.
 
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Hmm why would a distributor listing not include prices? I hope the 6800XT comes in at less than 500 (which is the rumoured 3070). I think 12 GB VRAM will be the sweet spot (for 1440p) for the next few years, as the new consoles are coming in with 16 GB shared memory. Current plan is 6800XT with custom water cooling; the dream is the card and a water block for sub 500.
 
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Yeah, well I remember that on launch day, AIB's had the number of CU completely wrong for Nvidia 30X0 GPUs

The number of CUs was correct, the number of shaders was supposedly unknown. Not that it matters, they don't even need to know those details.
 
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