Any idea if the HBM will be stacked on top? They connected HBM off to the sides with EMIB in the Xe-HPC package, but I haven't seen anything similar in the leaked delidded Sapphire Rapids photos.
Also... the Data Streaming Accelerator is an interesting addition. Its spec says it supports Optane. There is also an operation for flushing processor cache.
I wonder if the DSA is being used to maintain the processor cache coherency with accelerator memory when CXL bias ownership is flipped.
Also... the Data Streaming Accelerator is an interesting addition. Its spec says it supports Optane. There is also an operation for flushing processor cache.
I wonder if the DSA is being used to maintain the processor cache coherency with accelerator memory when CXL bias ownership is flipped.
