AMD Sampling Next-Gen Ryzen Desktop "Medusa Ridge," Sees Incremental IPC Upgrade, New cIOD

[Onasi]

I genuinely don't see what part of this would be burning money : if the main die is made small and self contained, they could put so many on a single wafer and if the CCD orders are grouped with TRs/Epycs as multipurpose CCDs, it would enjoy the economy of scale that comes with it instead of ordering specifically desktop-oriented CCDs and datacenter CCDs separately

In one case, AMD needs one CCD produced for everything that is fully scalable. It’s very simple (relatively speaking) since all it has are cores and cache. And the cIOD handles all SOC functions on the cheap depending on the desired end-product. What you suggest is making what amounts to a full-on SOC monolithic CPU on a cutting edge node AND those simple core and cache CCDs in addition AND a simplified cIOD for functions missing (for some reason) from the aforementioned SOC. Latter can even be sourced from a different fab company for maximum logistics and packaging nightmare. All that for… slightly better desktop performance for the plebs? Nah, I am good actually, fam.

 

[ARF]

Looking forward to it, would be nice if the consumers get a bump in core count again, we have had 16 core 32 thread parts since Ryzen 3000.

Yup, AMD is so late with this. And being late is a strategic mistake - literally they could have offered more cores and thrown Intel out of the market - instead they compete so-so and Intel is still the market leader.

I prefer an 8-core CPU with higher IPC per core. And with no E-cores.

Desktop apps need CPUs with high IPC per core, not CPUs with dozens of weak cores.

It simply doesn't work like so ^^^^. Windows requires more cores, otherwise with an octo-core you get micro-stutter every time when Windows launches another programme or a background process.

 

[rv8000]

How much of the powerdraw turned heat makes it to the backside exactly ?

current RAM are still shipped with either no heat spreader or just fancy looking ones, I think a small slab of aluminium would be more than enough to help heatsink a few degrees away from the ICs just through sheer radiation... plus, backside mobos don't have *no airflow*, it has *a little* which should still be enough to make a passive cooler of sort work well enough I reckon
an NVMe consumes max between 7W (gen4) to 12W (gen5) and you probably can figure out the size of the coolers we can find for those, just make it the same for CAMM2, just less tall and more spread out, even hanging off the module's board, that should be fine

I mean, low profile memory displaced to the back that sips power compared to DIMM, I'd buy
plus it would mean zero cooler incompatibilities, more space for bigger air coolers or a bulky water reservoir

The backside of a motherboard has no airflow unless youve got a dual chamber case, and even then the PSU is typically your only source of air movement and no where near where the socket/camm slot would be located. So effectively no airflow.

Then depending on tray cut-out size a heatsink wouldnt even fit between the tray or opening. Not only would you have to toss your motherboard for a camm one, but also replace and or modify your case. Additionally mobo manf. can’t make up their mind on a standard so far so I doubt socket placement will be the same, leaving potential case compatibility up in the air or a massive nuisance for the end user.

DDR5 at 1.45-1.5v (generally necessary for going 8000+) uses rougly 6w +\- last time I was paying attention to HW info. And even with decent/typical heatsinks (g.skill/corsair) you’re already hitting 45-50c+ spd sensor temp readouts (IC temps will be even higher). Higher than 50c is typically where you start to run into instability due to temperatures based on the refresh windows and general signal stability. A camm module directly behind the cpu would now also have to deal with the additional heat from the rear of the socket + even worse heatsinks (or none depending on case compatibility) AND no airflow. 8000+ at useful primary timings begins to require active cooling to maintain stability at that point. CAMM on the backside won’t solve a single thing in this regard.

All CAMM based mobos would do atm would be forcing users to pay more money for new parts for ZERO benefit, as CU-Dimms do everything and more that camm can do at this point in time.

And it’s painfully obvious this is the case as there are virtually no desktop boards or manf. supporting it at this time. It’s effectively DOA in the desktop space.

 

[Hecate91]

unfortunate, we'd stand to gain from that, I wonder what's "wrong" with desktop CAMM design that they won't commercialize it...

CAMM in laptops doesn't have much commercialization either, for some reason no one wants to use it.

If you don't want to spend more time arguing, just don't ignore reality when it doesn't suit your narrative and don't call my post misleading by saying that I am quoting second hand prices. I am quoting real pricing here for new parts. You are quoting MSRP prices of products that are released in a market where other products exist. Obviously when AMD, Intel, Nvidia, EVERYBODY has flooded the market with products, they will not price their new line of products in such a way that will make the older products impossible to sell. Are we going to throw logic in the trash just to create a point?

There isn't any point in arguing about it when they ignore reality, they're ignoring prices on newer products as well.

Yup, AMD is so late with this. And being late is a strategic mistake - literally they could have offered more cores and thrown Intel out of the market - instead they compete so-so and Intel is still the market leader.

It takes time to gain market share, in the June 2025 Steam HW survey AMD CPU's have 39% marketshare, AMD is getting there in the gaming and enthusiast market. But I think Intel will keep marketshare in the general consumer and corporate markets.

 

[user556]

No rdna 3.5 igpu upgrade on that iod nor an npu?
I have a hard time believing this will be all there is to zen 6

That's for the follow-up APUs, so not revealed as yet.

 

[Grebber01]

I SEE IT ! FINALLY, AFTER ALL THESE YEARS ! THE PROMISED LANDS OF CONSUMER QUAD CHANNEL !
I know it's still dual channel here for Zen6 but COME ON AMD, YOU CAN DO IT, MAKE IT THICKER AND GIVE US QUAD CHANNEL ON ZEN7

I mean, does anyone *really* need more ? the problem right now as it is the undoubtely *STUPID* amount of software that runs single-core/single-thread in this day and age
the still-too-few softwares that do run multi-core run fairly well and if you absolutely need more, Threadripper is there (though I'll be the first to admit it's definitely not a wallet friendly option)
though moving from 8 to 12 core CCDs is definitely nice for the mid-high end, as long as the price impact isn't too high...

always wondered why there wasn't more things going on backside, mobo mfers experimented putting M.2s backsides a few times but it's not a regular thing (yet ?) and zero cable projects put all the power connectors on the backside of the mobo (obviously), CAMM2 ought to go on the back of mobos, right ?

after a putting the cache below the CCD, better IMC, better interconnect, higher clocks across the board, AMD is cooking holy shit

well it's not all there will be to Zen6, I mentioned more of the Zen6 additions/changes above but tbh, I do hope the iGPU gets an upgrade along the IMC rebuild and they manage to sneak in an XDNA2 NPU (or maybe even XDNA3 ? who knows, I haven't heard much about XDNA development...)

it used to be an Intel tactic, I hope AMD won't adopt it...

I mean, 128 lanes of PCIe5 and quad/hexa/octachannel (I forgot how many are on current gen TRs) ECC memory is also a reason why you'd want such a platform to which Intel has no answer for besides Xeon that is massively expensive since server oriented instead of workstation

I mean, they might not increase the cache *per core* but they will likely increase the overall cache along the core count

5000 is on Zen3, it's a 2019 design, 6 years later, it's not that relevant anymore, the gap in IPC with Zen5 and soon-to-be Zen6 is huge already
also, 8000 series is a mobile design put in a desktop socket, it's not that surprising that it's cheap since not made to be really all that powerful

there's a lot of noise (because of a bunch of BIOS update patch notes) about 9000G coming to desktop apparently, maybe that's it ? always wanted to see at least Strix Point come to desktop and bring a thick iGPU (and honestly, a good NPU wouldn't be too bad either)

you'd need an IO controller on the CCD itself, kinda redundant tbh, not sure the improvement would be that significant, more interested in the better die interconnect that's also being added to Zen6

NPUs are a damn good thing... they make the processor unnecessarily expensive. Something with a nice 890M +15-20% more power

 

[Makaveli]

The question now is will you be able to drop zen 6 into a 600 or 800 series boards with DDR5 8000 support?

Or is there going to be a motherboard refresh?

 

[TheGeekn°72]

NPUs are a damn good thing... they make the processor unnecessarily expensive. Something with a nice 890M +15-20% more power

I'm pretty sure it's not the NPU in Strix point/halo that made them expensive, I can think of 4-5 other features that would, like, oh, idk, the massive iGPU and the quad channel, high bandwidth RAM ?

 

[Tek-Check]

does that mean IF is essentially an interCCD PCIe ?

No, but it has similar speed per single link.

 

[RootinTootinPootin]

Or is there going to be a motherboard refresh?

there should be one coming along, but should be backwards compatible, knowing AMD's track history this should be a given, though that 8000MT's support, I doubt that, current gen does that, but is limited/hard walled at 95GB's effective bandwidth when it should have been more.

 

[rv8000]

there should be one coming along, but should be backwards compatible, knowing AMD's track history this should be a given, though that 8000MT's support, I doubt that, current gen does that, but is limited/hard walled at 95GB's effective bandwidth when it should have been more.

New memory controller + faster fabric (hopefully) should solve that. Zen 4/5 already can hit higher bandwidth that 95gb, caveats including FCLK oc’s in most cases.

Not having full support on x8xx boards, or even x6xx boards, would be a HUGE let down. They promised socket support until 2027 so hopefully there aren’t any limitations using older boards.

 

[DemonicRyzen666]

you'd need an IO controller on the CCD itself, kinda redundant tbh, not sure the improvement would be that significant, more interested in the better die interconnect that's also being added to Zen6

No you don't, that's infinity link. Adding more infinity links to the substrate cost exponentially, & adding higher frequency's means they'll need to be closer together.
My issue is the CCD to CCD talks requites CCD to I/O then to the other CCD which is 100% pointless.
if the CCDs have just an infinity link to talk to each they no longer need to go out to the I/o die & back leaving less traffic in the I/o die.
Adding a second I/o die could help the infinity bottleneck problem or an "improved Infinity" but the link doesn't solve the main problem of the need for crosstalk.

 

[ymdhis]

The question now is will you be able to drop zen 6 into a 600 or 800 series boards with DDR5 8000 support?

Or is there going to be a motherboard refresh?

The DDR5 speeds depend largely on the IOD, so yeah. Assuming the board doesn't have bad signaling between the LGA and the DDR slots.

 

[ARF]

It takes time to gain market share, in the June 2025 Steam HW survey AMD CPU's have 39% marketshare, AMD is getting there in the gaming and enthusiast market. But I think Intel will keep marketshare in the general consumer and corporate markets.

Unfortunately, these numbers are about a very small, niche segment of the consumer market, which doesn't count the workstations, servers and supercomputers.
These are fake numbers.

It doesn't take time - it simply AMD's execution is broken.

 

[RootinTootinPootin]

Zen 4/5 already can hit higher bandwidth that 95gb, caveats including FCLK oc’s in most cases.

but couldn't take advantage of it on real world scenarios (unlike Intel's, its really scaling as it goes fast and higher), comparing 8000MT's on Intel platforms vs AMD's 8000MT's, AMD's feel like 7000MT's of what Intel does.

 

[rv8000]

but couldn't take advantage of it on real world scenarios (unlike Intel's, its really scaling as it goes fast and higher), comparing 8000MT's on Intel platforms vs AMD's 8000MT's, AMD's feel like 7000MT's of what Intel does.

If you take a look at both the Alder Lake cudimm excerpt and zen 5 memory scaling articles here it’s clear they both scale, so zen 5 can take advantage of more bandwidth. The architectures are obviously not 1:1 and different software reacts in different ways and more/less efficient in respective tests.

No need to make this about Intel vs. AMD, enough of that bs all over the forums.

 

[RootinTootinPootin]

so zen 5 can take advantage of more bandwidth

not so much I'd say with that crappy I/O die, the only thing hindering Zen 4 and 5 from "fully" utilizing those high bandwidths is that fabric clock (due to the limitations on I/O die and is highly silicon lottery in real world scenarios)

The architectures are obviously not 1:1 and different software reacts in different ways and more/less efficient in respective tests.

This..also how the code is written, optimized and compiled.

 

[ARF]

not so much I'd say with that crappy I/O die, the only thing hindering Zen 4 and 5 from "fully" utilizing those high bandwidths is that fabric clock (due to the limitations on I/O die and is highly silicon lottery in real world scenarios)

This..also how the code is written, optimized and compiled.

Then, why does Strix Point and Strix Halo work at DDR5 7500? What's the difference between the desktop Zen 5 and the mobile Zen 5?

 

[qcmadness]

there should be one coming along, but should be backwards compatible, knowing AMD's track history this should be a given, though that 8000MT's support, I doubt that, current gen does that, but is limited/hard walled at 95GB's effective bandwidth when it should have been more.

Yet higher bandwidth does not automatically translate to higher performance.

Various analyses of Zen 5 architecture also indicate that the bottleneck is elsewhere.

 

[phints]

Moving to a new TSMC process does allow higher density for higher core count so rumor seems reasonable. My guess is they'll go from 8c to 12c per CCD. That would make for a nice 9800X3D successor, although as we know games won't use much more than 8c. It'll need higher IPC and maybe ever more L3$ along with it to see gains.

 

[RootinTootinPootin]

Then, why does Strix Point and Strix Halo work at DDR5 7500? What's the difference between the desktop Zen 5 and the mobile Zen 5?

LPDDR5 != to DDR5, also the trash timings don't even make up for the memory speed bump..

Yet higher bandwidth does not automatically translate to higher performance.

Depends on the workload you do, I would take those analysis data with a whole grain of rock salt, its not even cross comparable as the system configs aren't apples to apples/near identical.

I have them all (ARL, RPL, Zen5), and for my daily normal needs and work needs the Intel Platforms gave me less headache to deal with, and performance is spot on and not all too diddy..

 

[ARF]

LPDDR5 != to DDR5, also the trash timings don't even make up for the memory speed bump..

? ?
DDR5 7500 = 120 GB/s memory thoughput, DDR5 6400 = 51.20 GB/s memory throughput.
Now, explain.

 

[RootinTootinPootin]

? ?

LP or Low Power Dimms if you want to get it spelled right, is not the same performance as your regular UDIMM DDR5's, since in nature the LPDDR5's use lower voltages, they need to be loosened up for timings to work out, stop depending on AI crap, you are more than capable of thinking this through.

clock for clock they aren't comparably equally faster, just on theoretical speeds but in real life scenarios, due to the much looser timings they are crap.

if you have seen my system specs on the ROG Ally, the same applies, DDR5 6400 on Desktop (UDIMM) isn't comparably same as LPDDR5 6400.

 

[kondamin]

That's for the follow-up APUs, so not revealed as yet.

They have a small 2CU integrated igpu zen 5 has rdna 2 like zen 4 had
Since it’s located on the same die the memory controller is at and that’s getting a refresh.
Beefing up the igpu would make sense

 

[user556]

They have a small 2CU integrated igpu zen 5 has rdna 2 like zen 4 had
Since it’s located on the same die the memory controller is at and that’s getting a refresh.
Beefing up the igpu would make sense

As long as it stays small in proportion I'll be happy. I'm glad AMD doesn't waste the die space. A 2D blitter is all that's needed for window compositing.